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    Subject[PATCH 7/8] x86/svm: Set IBPB when running a different VCPU
    Date
    From: Tom Lendacky <thomas.lendacky@amd.com>

    Set IBPB (Indirect Branch Prediction Barrier) when the current CPU is
    going to run a VCPU different from what was previously run. Nested
    virtualization uses the same VMCB for the second level guest, but the
    L1 hypervisor should be using IBRS to protect itself.

    Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
    ---
    arch/x86/kvm/svm.c | 31 +++++++++++++++++++++++++++++++
    1 file changed, 31 insertions(+)

    diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
    index 934a21e02e03..97126c2bd663 100644
    --- a/arch/x86/kvm/svm.c
    +++ b/arch/x86/kvm/svm.c
    @@ -289,6 +289,7 @@ struct amd_svm_iommu_ir {
    module_param(vgif, int, 0444);

    static bool __read_mostly have_spec_ctrl;
    +static bool __read_mostly have_ibpb_support;

    static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
    static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
    @@ -540,6 +541,7 @@ struct svm_cpu_data {
    struct kvm_ldttss_desc *tss_desc;

    struct page *save_area;
    + struct vmcb *current_vmcb;
    };

    static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
    @@ -1151,6 +1153,11 @@ static __init int svm_hardware_setup(void)
    pr_info("kvm: SPEC_CTRL available\n");
    else
    pr_info("kvm: SPEC_CTRL not available\n");
    + have_ibpb_support = have_spec_ctrl || cpu_has_ibpb_support();
    + if (have_ibpb_support)
    + pr_info("kvm: IBPB_SUPPORT available\n");
    + else
    + pr_info("kvm: IBPB_SUPPORT not available\n");

    return 0;

    @@ -1725,11 +1732,19 @@ static void svm_free_vcpu(struct kvm_vcpu *vcpu)
    __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
    kvm_vcpu_uninit(vcpu);
    kmem_cache_free(kvm_vcpu_cache, svm);
    +
    + /*
    + * The VMCB could be recycled, causing a false negative in
    + * svm_vcpu_load; block speculative execution.
    + */
    + if (have_ibpb_support)
    + wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
    }

    static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
    {
    struct vcpu_svm *svm = to_svm(vcpu);
    + struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
    int i;

    if (unlikely(cpu != vcpu->cpu)) {
    @@ -1758,6 +1773,12 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
    if (static_cpu_has(X86_FEATURE_RDTSCP))
    wrmsrl(MSR_TSC_AUX, svm->tsc_aux);

    + if (sd->current_vmcb != svm->vmcb) {
    + sd->current_vmcb = svm->vmcb;
    + if (have_ibpb_support)
    + wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
    + }
    +
    avic_vcpu_load(vcpu, cpu);
    }

    @@ -2798,6 +2819,11 @@ static int nested_svm_vmexit(struct vcpu_svm *svm)
    if (!nested_vmcb)
    return 1;

    + /*
    + * No need for IBPB here, the L1 hypervisor should be running with
    + * IBRS=1 and inserts one already when switching L2 VMs.
    + */
    +
    /* Exit Guest-Mode */
    leave_guest_mode(&svm->vcpu);
    svm->nested.vmcb = 0;
    @@ -3061,6 +3087,11 @@ static bool nested_svm_vmrun(struct vcpu_svm *svm)
    if (!nested_vmcb)
    return false;

    + /*
    + * No need for IBPB here, since the nested VM is less privileged. The
    + * L1 hypervisor inserts one already when switching L2 VMs.
    + */
    +
    if (!nested_vmcb_checks(nested_vmcb)) {
    nested_vmcb->control.exit_code = SVM_EXIT_ERR;
    nested_vmcb->control.exit_code_hi = 0;
    --
    1.8.3.1

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