Messages in this thread | | | Subject | Re: [PATCH] clk: meson: axg: fix the od shift of the sys_pll | From | Jerome Brunet <> | Date | Tue, 30 Jan 2018 20:12:06 +0100 |
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On Fri, 2018-01-19 at 10:09 +0800, Yixun Lan wrote: > According to datasheet, the od shift of sys_pll is 16, > fix the typo which introduced at previous commit. > > Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers') > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Applied to clk-meson next/drivers after fixing the commit message a bit Thx
Jerome
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