Messages in this thread | | | Date | Fri, 26 Jan 2018 16:33:39 -0800 | From | Stephen Boyd <> | Subject | Re: [PATCH] clk: aspeed: Handle inverse polarity of USB port 1 clock gate |
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On 01/12, Benjamin Herrenschmidt wrote: > The USB port 1 clock gate control has an inversed polarity > from all the other clock gates in the chip. This makes the > aspeed_clk_{enable,disable} functions honor the flag > CLK_GATE_SET_TO_DISABLE and set that flag appropriately > so it's set for all clocks except USB port 1. > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > -- > > I chose not to add a column to the table for that one special > case. If future chips start growing more of these, we should > consider adding this to the table instead. > > Without this, USB port 1 doesn't work properly with the new > clk driver. > > ---
Applied to clk-next
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