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    Subject[PATCH v3 4/6] x86/msr: Add definitions for new speculation control MSRs
    Date
    Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES.

    See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf

    Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
    ---
    arch/x86/include/asm/msr-index.h | 12 ++++++++++++
    1 file changed, 12 insertions(+)

    diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
    index fa11fb1..eb83ff1 100644
    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -39,6 +39,13 @@

    /* Intel MSRs. Some also available on other CPUs */

    +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
    +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */
    +#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */
    +
    +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
    +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */
    +
    #define MSR_PPIN_CTL 0x0000004e
    #define MSR_PPIN 0x0000004f

    @@ -57,6 +64,11 @@
    #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)

    #define MSR_MTRRcap 0x000000fe
    +
    +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
    +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
    +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
    +
    #define MSR_IA32_BBL_CR_CTL 0x00000119
    #define MSR_IA32_BBL_CR_CTL3 0x0000011e

    --
    2.7.4
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