Messages in this thread | | | From | Joel Stanley <> | Date | Thu, 28 Sep 2017 14:29:22 +1000 | Subject | Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs |
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On Wed, Sep 27, 2017 at 5:34 PM, Andrew Jeffery <andrew@aj.id.au> wrote: > On Wed, 2017-09-27 at 16:13 +1000, Joel Stanley wrote: >> > > + div_table, >> > >> > This doesn't seem to be correct. There's the problem of 0b000 and 0b001 mapping >> > the same value of 2 for the AST2500, whose table then increments in steps of 1. >> > The AST2400 mapping on the otherhand is multiples of 2 starting at 2, with no >> > inconsistency for 0b000 vs 0b001. >> >> Yep, we do use a different table for ast2400 vs ast2500. See >> ast2400_div_table vs ast2500_div_table. > > Yep, but for the AST2500 this is a different table again to what you've > already defined (for the AST2500). However, for the AST2400 the table > looks the same as the other AST2400 tables.
You're right. I didn't realise you were pointing out something strange about eclk.
I added another table for eclk, and the correct one is selected by the platform data.
I'll send out v4 today if no more reviews come in.
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