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    Subject[PATCH for 4.9 06/59] clk: sunxi-ng: fix PLL_CPUX adjusting on H3
    Date
    From: Ondrej Jirman <megous@megous.com>

    [ Upstream commit a43c96427e713bea94e9ef50e8be1f493afc0691 ]

    When adjusting PLL_CPUX on H3, the PLL is temporarily driven
    too high, and the system becomes unstable (oopses or hangs).

    Add a notifier to avoid this situation by temporarily switching
    to a known stable 24 MHz oscillator.

    Signed-off-by: Ondrej Jirman <megous@megous.com>
    Tested-by: Lutz Sammer <johns98@gmx.net>
    Acked-by: Chen-Yu Tsai <wens@csie.org>
    Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
    Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
    ---
    drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 10 ++++++++++
    1 file changed, 10 insertions(+)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
    index 21c427d86f28..a26c8a19fe93 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
    @@ -803,6 +803,13 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
    .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
    };

    +static struct ccu_mux_nb sun8i_h3_cpu_nb = {
    + .common = &cpux_clk.common,
    + .cm = &cpux_clk.mux,
    + .delay_us = 1, /* > 8 clock cycles at 24 MHz */
    + .bypass_index = 1, /* index of 24 MHz oscillator */
    +};
    +
    static void __init sun8i_h3_ccu_setup(struct device_node *node)
    {
    void __iomem *reg;
    @@ -821,6 +828,9 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
    writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);

    sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
    +
    + ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
    + &sun8i_h3_cpu_nb);
    }
    CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
    sun8i_h3_ccu_setup);
    --
    2.11.0
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