Messages in this thread | | | Date | Tue, 25 Jul 2017 17:36:50 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change |
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On 07/23, Icenowy Zheng wrote: > From: Chen-Yu Tsai <wens@csie.org> > > This patch utilizes the new PLL clk notifier to gate then ungate the > PLL CPU clock after rate changes. This should prevent any system hangs > resulting from cpufreq changes to the clk. > > Reported-by: Ondrej Jirman <megous@megous.com> > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > Tested-by: Icenowy Zheng <icenowy@aosc.io> > ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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