Messages in this thread Patch in this message | | | From | Mikko Perttunen <> | Subject | [PATCH v3 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster | Date | Mon, 12 Jun 2017 13:23:04 +0300 |
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The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt new file mode 100644 index 000000000000..0c80cd8ee839 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt @@ -0,0 +1,20 @@ +NVIDIA Tegra CCPLEX_CLUSTER area + +The Tegra186 CCPLEX_CLUSTER area contains memory-mapped +registers that initiate CPU frequency/voltage transitions. + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra186-ccplex-cluster": for Tegra186 +- reg: Must contain an (offset, length) pair of the device's MMIO + register area +- nvidia,bpmp: phandle to BPMP device that can be queried for OPP tables + +Example: + + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x3fffff>, + + nvidia,bpmp = <&bpmp>; + }; -- 2.1.4
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