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SubjectRe: [PATCH v5 2/2] iio: Aspeed ADC
On 05/04/17 22:50, Stephen Boyd wrote:
> On 04/01, Jonathan Cameron wrote:
>> On 28/03/17 22:52, Rick Altherr wrote:
>>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>>> interrupts are supported by the hardware but are not currently implemented.
>>> Signed-off-by: Rick Altherr <>
>> Two really trivial things inline. I'll fix them whilst applying rather than
>> having you do a v6 - please do sanity check I haven't messed it up though!
>> Applied to the togreg branch of iio.git and pushed out as testing for
>> the autobuilders to play with it.
> Oh I was too late. Blame work. Anyway, I made some comments on
> v4. If they're fixed in a later patch or discussed on list that's
> fine. No worries on my end.
Oops. I went a bit quick on this one I guess.

Anyhow, from a quick read of your comments I'm not sure if any of
them are such that we should revert. Perhaps we Rick can prepare
a follow up patch covering them? I got a little lost so am not
sure but if there is anything effecting bindings Rick, please
get this through asap or let me know if we need to revert for now.
Even if it is a case of adding a bit of binding and following up
with the code using it a bit later.

I'd asked for input on the clock stuff then forgot all about it on
the later version. Sorry about that!


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