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SubjectRE: [PATCH] serial: tegra: Map the iir register to default defines
Verification failed on Tegra.
Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled.
while (1) {
iir = tegra_uart_read(tup, UART_IIR);
+iir &= UART_IIR_MASK;


-----Original Message-----
From: Laxman Dewangan
Sent: Thursday, March 30, 2017 3:48 PM
To: Olliver Schinagl <>; Greg Kroah-Hartman <>; Jiri Slaby <>; Stephen Warren <>; Thierry Reding <>; Alexandre Courbot <>
Cc:;;; Shardar Mohammed <>
Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines

On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End
> of Data interrupt.
> Signed-off-by: Olliver Schinagl <>
> ---

Adding Shardar for verifications.

Acked-by: Laxman Dewangan <>

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