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SubjectRe: [PATCH 0/6] x86: 5-level paging enabling for v4.12, Part 1
On Tue, Mar 14, 2017 at 12:47 AM, Ingo Molnar <> wrote:
> I've also applied the GUP patch, with the assumption that you'll address Linus's
> request to switch x86 over to the generic version.

Note that switching over to the generic version is somewhat fraught
with subtle issues:

(a) we need to make sure that x86 actually matches the required
semantics for the generic GUP.

(b) we need to make sure the atomicity of the page table reads is ok.

(c) need to verify the maximum VM address properly

I _think_ (a) is ok. The code (and the config option name) talks about
freeing page tables using RCU, but in fact I don't think it relies on
it, and it's sufficient that it disables interrupts and that that will
block any IPI's.

In contrast, I think (b) needs real work to make sure it's ok on
32-bit PAE with 64-bit pte entries. The generic code currently just
does READ_ONCE(), while the x86 code does gup_get_pte().

And (c) means that we need to really replace that generic code that
does "access_ok()": with a proper check against maximum user address
(ie independent of set_fs(KERNEL_DS)).

But it would be good to aim for unifying this part of the VM,
considering how many bugs we've had in GUP. The latest 5-level typo
has not been the only one. It's clearly more subtle than you'd think.

So it's not quite as simple as just "switching over". I think we need
to introduce that gup_get_pte() to all the generic users, and we need
to introduce a "user address limit" for those architectures too.


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