Messages in this thread | | | Date | Thu, 28 Dec 2017 16:01:24 -0800 | From | Stephen Boyd <> | Subject | Re: [PATCH v11 3/6] clk: qcom: Add A53 PLL support |
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On 12/05, Georgi Djakov wrote: > The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, > a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources > are connected to a mux and half-integer divider, which is feeding the > CPU cores. > > This patch adds support for the primary CPU PLL which generates the > higher range of frequencies above 1GHz. > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> > Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> > ---
Applied to clk-next
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