| Date | Thu, 21 Dec 2017 16:23:54 -0800 | From | Stephen Boyd <> | Subject | Re: [PATCH v2 03/11] clk: qcom: ipq8074: fix missing GPLL0 divider width |
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On 12/13, Abhishek Sahu wrote: > GPLL0 uses 4 bits post divider which should be specified > in clock driver structure. > > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> > ---
Applied to clk-next
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