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    Subject[PATCH 4.9 06/87] ARM: dts: imx53-qsb-common: fix FEC pinmux config
    Date
    4.9-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Patrick Bruenn <p.bruenn@beckhoff.com>


    [ Upstream commit 8b649e426336d7d4800ff9c82858328f4215ba01 ]

    The pinmux configuration in device tree was different from manual
    muxing in <u-boot>/board/freescale/mx53loco/mx53loco.c
    All pins were configured as NO_PAD_CTL(1 << 31), which was fine as the
    bootloader already did the correct pinmuxing for us.
    But recently u-boot is migrating to reuse device tree files from the
    kernel tree, so it seems to be better to have the correct pinmuxing in
    our files, too.

    Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/arm/boot/dts/imx53-qsb-common.dtsi | 20 ++++++++++----------
    1 file changed, 10 insertions(+), 10 deletions(-)

    --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
    +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
    @@ -215,16 +215,16 @@

    pinctrl_fec: fecgrp {
    fsl,pins = <
    - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
    - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
    - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
    - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
    - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
    - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
    - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
    - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
    - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
    - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
    + MX53_PAD_FEC_MDC__FEC_MDC 0x4
    + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
    + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
    + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
    + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
    + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
    + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
    + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
    + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
    + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
    >;
    };


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