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SubjectRe: [PATCH V0 2/3] perf/x86/intel/bm.c: Add Intel Branch Monitoring support
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On Mon, 2017-11-06 at 13:49 +0200, Alexander Shishkin wrote:
> On Fri, Nov 03, 2017 at 11:00:05AM -0700, Megha Dey wrote:
> > +static int intel_bm_event_init(struct perf_event *event)
> > +{
>
> ...
>
> > + /*
> > + * Find a hardware counter for the target task
> > + */
> > + for (i = 0; i < bm_num_counters; i++) {
> > + if ((bm_counter_owner[i] == NULL) ||
> > + (bm_counter_owner[i]->state == PERF_EVENT_STATE_DEAD)) {
> > + counter_to_use = i;
> > + bm_counter_owner[i] = event;
> > + break;
>
> How are two concurrent perf_event_open()s not going to race here?
> Also, I'm not sure what's the value of looking at the ->state here.
> Shouldn't the ->destroy() method clear the corresponding array slot?

Yes you are right. I will add a locking mechanism here to prevent racing
and remove the ->state in the next version.
>
> > + }
> > + }
>
> ...
>
> > + wrmsrl(BR_DETECT_COUNTER_CONFIG_BASE + counter_to_use,
> > + event->hw.bm_counter_conf);
> > + wrmsrl(BR_DETECT_STATUS_MSR, 0);
>
> These wrmsrs will happen on whatever CPU perf_event_open() is called on,
> as opposed to the CPU where the event will be scheduled. You probably want
> to keep the MSR accesses in the start()/stop() callbacks.

Agreed, don't think we need this code here. We are writing to the MSRs
in start() anyways.
>
> Regards,
> --
> Alex
>


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