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    SubjectRe: [PATCH 04/23] x86, tlb: make CR4-based TLB flushes more robust
    On Tue, 31 Oct 2017, Dave Hansen wrote:
    > Our CR4-based TLB flush currently requries global pages to be
    > supported *and* enabled. But, we really only need for them to be
    > supported. Make the code more robust by alllowing X86_CR4_PGE to
    > clear as well as set.

    That's not what the patch is actually doing.

    > cr4 = this_cpu_read(cpu_tlbstate.cr4);
    > - /* clear PGE */
    > - native_write_cr4(cr4 & ~X86_CR4_PGE);
    > - /* write old PGE again and flush TLBs */
    > + /*
    > + * This function is only called on systems that support X86_CR4_PGE
    > + * and where always set X86_CR4_PGE. Warn if we are called without
    > + * PGE set.
    > + */
    > + WARN_ON_ONCE(!(cr4 & X86_CR4_PGE));

    Because if CR4_PGE is not set, this warning triggers. So this defeats the
    toggle mode you are implementing.

    > + /*
    > + * Architecturally, any _change_ to X86_CR4_PGE will fully flush the
    > + * TLB of all entries including all entries in all PCIDs and all
    > + * global pages. Make sure that we _change_ the bit, regardless of
    > + * whether we had X86_CR4_PGE set in the first place.
    > + */
    > + native_write_cr4(cr4 ^ X86_CR4_PGE);
    > + /* Put original CR3 value back: */

    That want's to be CR4. Restoring CR3 to CR4 might be suboptimal.

    > native_write_cr4(cr4);

    Thanks,

    tglx

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