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    Subject[PATCH v2 09/10] arm64: allwinner: a64: add DE2 CCU for A64 SoC
    Date
    The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
    section of SRAM (SRAM C) to be accessed.

    Adds the device tree nodes for the SRAM controller and the DE2 CCU.

    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
    ---
    arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34 +++++++++++++++++++++++++++
    1 file changed, 34 insertions(+)

    diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
    index 062040ec2fed..03a46da0f0fa 100644
    --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
    +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
    @@ -130,6 +130,40 @@
    #size-cells = <1>;
    ranges;

    + display_clocks: clock@1000000 {
    + compatible = "allwinner,sun50i-a64-de2-clk";
    + reg = <0x01000000 0x100000>;
    + clocks = <&ccu CLK_DE>,
    + <&ccu CLK_BUS_DE>;
    + clock-names = "mod",
    + "bus";
    + resets = <&ccu RST_BUS_DE>;
    + allwinner,sram = <&de2_sram>;
    + #clock-cells = <1>;
    + #reset-cells = <1>;
    + };
    +
    + sram-controller@1c00000 {
    + compatible = "allwinner,sun50i-a64-sram-controller";
    + reg = <0x01c00000 0x1000>;
    + #address-cells = <1>;
    + #size-cells = <1>;
    + ranges;
    +
    + sram_c: sram@18000 {
    + compatible = "mmio-sram";
    + reg = <0x00018000 0x28000>;
    + #address-cells = <1>;
    + #size-cells = <1>;
    + ranges = <0 0x00018000 0x28000>;
    +
    + de2_sram: sram-section@0 {
    + compatible = "allwinner,sun50i-a64-sram-c";
    + reg = <0x0000 0x28000>;
    + };
    + };
    + };
    +
    syscon: syscon@1c00000 {
    compatible = "allwinner,sun50i-a64-system-controller",
    "syscon";
    --
    2.13.6
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