Messages in this thread Patch in this message | | | From | Ioana Radulescu <> | Subject | [PATCH 3/9] staging: fsl-dpaa2/eth: Check SGT final bit is present | Date | Wed, 11 Oct 2017 08:29:45 -0500 |
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For scatter-gather ingress frames, we expect to receive a list of fragments from the hardware, last of which is marked with a "final" bit.
Add a check to make sure the Rx frame has this bit set correctly; there's not much we can do in case of a malformed frame, but at least issue a warning.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> --- drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c index e9fe1c9..6f009d1 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c @@ -213,6 +213,8 @@ static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv, break; } + WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT"); + /* Count all data buffers + SG table buffer */ ch->buf_count -= i + 2; -- 2.7.4
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