Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | From | Andrey Pronin <> | Subject | [PATCH 1/2] tpm: devicetree: document properties for cr50 | Date | Thu, 14 Jul 2016 19:20:17 -0700 |
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Add TPM2.0-compatible interface to Cr50. Document its properties in devicetree.
Signed-off-by: Andrey Pronin <apronin@chromium.org> --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt
diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..1b05e51 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,30 @@ +* Cr50 Chip on SPI. + +TCG PTP FIFO Compliant Interface to Cr50 on SPI bus. + +Required properties: +- compatible: Should be "google,cr50_spi". +- spi-max-frequency: Maximum SPI frequency. + +Optional properties: +- access-delay-msec: Required delay between subsequent transactions on SPI. +- sleep-delay-msec: Time after the last SPI activity, after which the chip + may go to sleep. +- wake-start-delay-msec: Time after initiating wake up before the chip is + ready to accept commands over SPI. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50_spi"; + reg = <0>; + spi-max-frequency = <800000>; + + access-delay-msec = <2>; + sleep-delay-msec = <1000>; + wake-start-delay-msec = <60>; + }; +}; -- 2.6.6
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