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SubjectRe: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
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From: Jisheng Zhang <jszhang@marvell.com>
Date: Wed, 30 Mar 2016 19:55:21 +0800

> The mvneta is also used in some Marvell berlin family SoCs which may
> have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
> usage with L1_CACHE_BYTES.
>
> And since dma_alloc_coherent() is always cacheline size aligned, so
> remove the align checks.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>

Applied.

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