Messages in this thread | | | Subject | Re: [PART1 RFC v2 03/10] svm: Introduce new AVIC VMCB registers | From | Suravee Suthikulpanit <> | Date | Mon, 14 Mar 2016 14:41:55 +0700 |
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Hi,
On 03/07/2016 10:44 PM, Paolo Bonzini wrote: > > On 04/03/2016 21:46, Suravee Suthikulpanit wrote: >> >From: Suravee Suthikulpanit<suravee.suthikulpanit@amd.com> >> > >> >Introduce new AVIC VMCB registers. Also breakdown int_ctl register >> >into bit-field for ease of use. >> > >> >Signed-off-by: Suravee Suthikulpanit<suravee.suthikulpanit@amd.com> >> >--- >> > arch/x86/include/asm/svm.h | 29 ++++++++++++++++++++++++----- >> > 1 file changed, 24 insertions(+), 5 deletions(-) >> > >> >diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h >> >index 6136d99..db5d7af 100644 >> >--- a/arch/x86/include/asm/svm.h >> >+++ b/arch/x86/include/asm/svm.h >> >@@ -67,10 +67,24 @@ struct __attribute__ ((__packed__)) vmcb_control_area { >> > u32 asid; >> > u8 tlb_ctl; >> > u8 reserved_2[3]; >> >- u32 int_ctl; >> >+ union { /* Offset 0x60 */ >> >+ u32 int_ctl; >> >+ >> >+ struct __attribute__ ((__packed__)) { >> >+ u32 v_tpr : 8, >> >+ v_irq : 1, >> >+ reserved_3 : 7, >> >+ v_intr_prio : 4, >> >+ v_ign_tpr : 1, >> >+ reserved_4 : 3, >> >+ v_intr_masking : 1, >> >+ reserved_5 : 6, >> >+ avic_enable : 1; > Please do not introduce bitfields and drop patch 4. > > Thanks, > > Paolo >
Any particular reason why you do not recommend the use of bit field?
Thanks, Suravee
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