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    Subject[PATCH 4.4 220/342] drm/i915: Make sure DC writes are coherent on flush.
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Francisco Jerez <currojerez@riseup.net>

    commit 935a0ff0e1ea62a116848c0a187b13838f7b9cee upstream.

    We need to set the DC FLUSH PIPE_CONTROL bit on Gen7+ to guarantee
    that writes performed via the HDC are visible in memory. Fixes an
    intermittent failure in a Piglit test that writes to a BO from a
    shader using GL atomic counters (implemented as HDC untyped atomics)
    and then expects the memory to read back the same value after mapping
    it on the CPU.

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91298
    Tested-by: Mark Janes <mark.a.janes@intel.com>
    Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: Francisco Jerez <currojerez@riseup.net>
    Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/1452740379-3194-1-git-send-email-currojerez@riseup.net
    (cherry picked from commit 965fd602a6436f689f4f2fe40a6789582778ccd5)
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/i915/intel_lrc.c | 1 +
    drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
    2 files changed, 3 insertions(+)

    --- a/drivers/gpu/drm/i915/intel_lrc.c
    +++ b/drivers/gpu/drm/i915/intel_lrc.c
    @@ -1706,6 +1706,7 @@ static int gen8_emit_flush_render(struct
    if (flush_domains) {
    flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
    flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
    + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
    flags |= PIPE_CONTROL_FLUSH_ENABLE;
    }

    --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
    +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
    @@ -347,6 +347,7 @@ gen7_render_ring_flush(struct drm_i915_g
    if (flush_domains) {
    flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
    flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
    + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
    flags |= PIPE_CONTROL_FLUSH_ENABLE;
    }
    if (invalidate_domains) {
    @@ -419,6 +420,7 @@ gen8_render_ring_flush(struct drm_i915_g
    if (flush_domains) {
    flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
    flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
    + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
    flags |= PIPE_CONTROL_FLUSH_ENABLE;
    }
    if (invalidate_domains) {
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