Messages in this thread | | | Date | Thu, 11 Feb 2016 12:35:54 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCHv10 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support |
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On Wed, Feb 10, 2016 at 01:26:21PM -0600, tthayer@opensource.altera.com wrote: > From: Thor Thayer <tthayer@opensource.altera.com> > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > > Each type of ECC is individually configurable.
All 4 applied, thanks.
-- Regards/Gruss, Boris.
ECO tip #101: Trim your mails when you reply.
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