Messages in this thread | ![/](/images/icornerl.gif) | | Date | Thu, 22 Dec 2016 15:03:45 -0600 | From | Rob Herring <> | Subject | Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers |
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On Tue, Dec 20, 2016 at 06:05:48PM +1030, Andrew Jeffery wrote: > The System Control Unit IP block in the Aspeed SoCs is typically where > the pinmux configuration is found, but not always. A number of pins > depend on state in one of LPC Host Control (LHC) or SoC Display > Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the > means to adjust these as necessary. > > We use syscon to cast a regmap over the GFX and LPC blocks, which is > used as an arbitration layer between the relevant driver and the pinctrl > subsystem. The regmaps are then exposed to the SoC-specific pinctrl > drivers by phandles in the devicetree, and are selected during a mux > request by querying a new 'ip' member in struct aspeed_sig_desc. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Reviewed-by: Joel Stanley <joel@jms.id.au> > --- > > Joel: I kept your r-b tag here despite reworking the g5 example bindings, as > you've given your r-b for the lpc bindings which are what I have added. > > .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 80 ++++++++--
Acked-by: Rob Herring <robh@kernel.org>
> drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 18 +-- > drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 48 ++++-- > drivers/pinctrl/aspeed/pinctrl-aspeed.c | 161 +++++++++++++-------- > drivers/pinctrl/aspeed/pinctrl-aspeed.h | 32 ++-- > 5 files changed, 242 insertions(+), 97 deletions(-)
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