| Date | Wed, 21 Dec 2016 16:11:20 -0800 | From | Stephen Boyd <> | Subject | Re: [PATCH v4 7/9] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board |
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On 12/13, gabriel.fernandez@st.com wrote: > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or > from pll-sai-p. > > The SDIO clock could be also derived from 48Mhz or from sys clock. > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> > ---
Applied to clk-stm32f4 and merged into clk-next
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