Messages in this thread | | | From | Bartosz Golaszewski <> | Date | Fri, 2 Dec 2016 14:09:09 +0100 | Subject | Re: [PATCH 3/3] ARM: da850: fix da850_set_pll0rate() |
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2016-12-02 12:20 GMT+01:00 Sekhar Nori <nsekhar@ti.com>: > On Thursday 01 December 2016 10:45 PM, Bartosz Golaszewski wrote: >> This function is broken - its second argument is an index to the freq >> table, not the requested clock rate in Hz. It leads to an oops when >> called from clk_set_rate() since this argument isn't bounds checked >> either. >> >> Fix it by iterating over the array of supported frequencies and >> selecting a one that matches or returning -EINVAL for unsupported >> rates. >> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> > > When this function was written, it was written for speed. The only user > of setting pll0 rate is drivers/cpufreq/davinci-cpufreq.c (not sure how > you were trying to set pll0 rate). And that driver directly passes the > table index to the set_rate() function. >
Hi Sekhar, thanks for the hints.
The origin of this series is the default pll0 frequency set by upstream u-boot which caused FIFO underflows in LCDC even with the pixel clock well below 37.5 MHz. I had already sent a patch to the u-boot mailing list, but thought I'd try setting the clock from within tilcdc code. This is when I stumbled upon this issue.
I'll send a v2 of this series.
Thanks, Bartosz Golaszewski
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