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    Subject[tip:perf/core] perf/x86: Fix LBR related crashes on Intel Atom
    Commit-ID:  6fc2e83077b05a061afe9b24f2fdff7a0434eb67
    Gitweb: http://git.kernel.org/tip/6fc2e83077b05a061afe9b24f2fdff7a0434eb67
    Author: Stephane Eranian <eranian@google.com>
    AuthorDate: Thu, 3 Dec 2015 23:33:17 +0100
    Committer: Ingo Molnar <mingo@kernel.org>
    CommitDate: Wed, 6 Jan 2016 11:15:33 +0100

    perf/x86: Fix LBR related crashes on Intel Atom

    This patches fixes the LBR kernel crashes on Intel Atom.

    The kernel was assuming that if the CPU supports 64-bit format
    LBR, then it has an LBR_SELECT MSR. Atom uses 64-bit LBR format
    but does not have LBR_SELECT. That was causing NULL pointer
    dereferences in a couple of places.

    Signed-off-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Cc: kan.liang@intel.com
    Fixes: 96f3eda67fcf ("perf/x86/intel: Fix static checker warning in lbr enable")
    Link: http://lkml.kernel.org/r/1449182000-31524-2-git-send-email-eranian@google.com
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    ---
    arch/x86/kernel/cpu/perf_event_intel_lbr.c | 11 +++++++----
    1 file changed, 7 insertions(+), 4 deletions(-)

    diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    index e2fad0c..1390148 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    @@ -161,7 +161,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
    */
    if (cpuc->lbr_sel)
    lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
    - if (!pmi)
    + if (!pmi && cpuc->lbr_sel)
    wrmsrl(MSR_LBR_SELECT, lbr_select);

    rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
    @@ -430,7 +430,7 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
    */
    static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
    {
    - bool need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
    + bool need_info = false;
    unsigned long mask = x86_pmu.lbr_nr - 1;
    int lbr_format = x86_pmu.intel_cap.lbr_format;
    u64 tos = intel_pmu_lbr_tos();
    @@ -438,8 +438,11 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
    int out = 0;
    int num = x86_pmu.lbr_nr;

    - if (cpuc->lbr_sel->config & LBR_CALL_STACK)
    - num = tos;
    + if (cpuc->lbr_sel) {
    + need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
    + if (cpuc->lbr_sel->config & LBR_CALL_STACK)
    + num = tos;
    + }

    for (i = 0; i < num; i++) {
    unsigned long lbr_idx = (tos - i) & mask;

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