Messages in this thread | | | Subject | Re: [PATCH 1/3] ASoC: fsl_ssi: mark SACNT register volatile | From | Timur Tabi <> | Date | Sun, 10 Jan 2016 15:33:55 -0600 |
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Maciej S. Szmigiero wrote: > + regmap_write(regs, CCSR_SSI_SACNT, > + ssi_private->regcache_sacnt);
So I'm not familiar with all of the regcache features, but I understand this patch. I was wondering if it makes sense to write the same exact value that was read previously. Isn't it possible for the WR or RD bits to change between fsl_ssi_suspend() and fsl_ssi_resume()? That is, should we be doing this instead?
u32 temp; regmap_read(regs, CCSR_SSI_SACNT, &temp); temp &= 0x18; // preserve WR and RD regmap_write(regs, CCSR_SSI_SACNT, (ssi_private->regcache_sacnt & ~0x18) | temp);
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