Messages in this thread | | | Date | Tue, 8 Sep 2015 20:39:37 -0700 | From | Andi Kleen <> | Subject | Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write |
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> Hmm, I didn't mean mfence can't serialize the instructions. For a true > IO, a serialization can't guarantee device finishes the IO, we generally > read some safe IO registers to wait IO finish. I completely don't know > if this case fits here though.
Sorry for the late answer. We (Intel) analyzed this case in detail and can confirm that the following sequence
1. Memory-mapped write to LVT Timer Register, setting bits 18:17 to 10b. 23. MFENCE. 4. WRMSR to the IA32_TSC_DEADLINE MSR the desired deadline.
has the same effect as the loop algorithm described in the SDM on all Intel CPUs. So it's fine to use MFENCE here.
-Andi
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