Messages in this thread | | | From | Andy Lutomirski <> | Date | Mon, 7 Sep 2015 10:22:56 -0700 | Subject | Re: Dealing with the NMI mess |
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On Mon, Sep 7, 2015 at 10:01 AM, Maciej W. Rozycki <macro@linux-mips.org> wrote: > These are all implementation-specific details, including the INT1 > instruction, which is why I am not at all surprised that they are omitted > from architecture manuals.
That bit is BS, though. The INT1 instruction, executed in user mode (CPL3) with no hardware debugger attached, will enter the kernel through a gate at vector 1, *even if that gate has DPL == 0*.
If there's an instruction that bypasses hardware protection mechanisms, then Intel should document it rather than relying on OS writers to know enough folklore to get it right.
Heck, SDM Volume 3 6.12.1.1 says "The processor checks the DPL of the interrupt or trap gate only if an exception or interrupt is generated with an INT n, INT 3, or INTO instruction." It does not say "the processor does not check the DPL of the interrupt or trap gate if the exception or interrupt is generated with the undocumented ICEBP instruction."
--Andy
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