Messages in this thread Patch in this message | | | From | Roger Quadros <> | Subject | [PATCH v3 21/27] ARM: dts: dra7x-evm: Provide NAND ready pin | Date | Fri, 18 Sep 2015 17:53:43 +0300 |
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On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s. Write speed was unchanged at 7123 KiB/s. Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros <rogerq@ti.com> --- arch/arm/boot/dts/dra7-evm.dts | 1 + arch/arm/boot/dts/dra72-evm.dts | 1 + 2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 8a31161..4760562 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -591,6 +591,7 @@ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 245f5f9..a11a646 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -405,6 +405,7 @@ reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; -- 2.1.4
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