Messages in this thread | | | Date | Tue, 1 Sep 2015 14:45:40 -0700 | From | "Paul E. McKenney" <> | Subject | Re: [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants |
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On Tue, Sep 01, 2015 at 08:00:27PM +0100, Will Deacon wrote: > On Fri, Aug 28, 2015 at 04:39:21PM +0100, Peter Zijlstra wrote: > > On Fri, Aug 28, 2015 at 10:16:02PM +0800, Boqun Feng wrote: > > > Ah.. just read through the thread you mentioned, I might misunderstand > > > you, probably because I didn't understand RCpc well.. > > > > > > You are saying that in a RELEASE we -might- switch from smp_lwsync() to > > > smp_mb() semantically, right? I guess this means we -might- switch from > > > RCpc to RCsc, right? > > > > > > If so, I think I'd better to wait until we have a conclusion for this. > > > > Yes, the difference between RCpc and RCsc is in the meaning of RELEASE + > > ACQUIRE. With RCsc that implies a full memory barrier, with RCpc it does > > not. > > We've discussed this before, but for the sake of completeness, I don't > think we're fully RCsc either because we don't order the actual RELEASE > operation again a subsequent ACQUIRE operation: > > P0 > smp_store_release(&x, 1); > foo = smp_load_acquire(&y); > > P1 > smp_store_release(&y, 1); > bar = smp_load_acquire(&x); > > We allow foo == bar == 0, which is prohibited by SC.
I certainly hope that no one expects foo == bar == 0 to be prohibited!!!
On the other hand, in this case, foo == bar == 1 will be prohibited:
P0 foo = smp_load_acquire(&y); smp_store_release(&x, 1);
P1 bar = smp_load_acquire(&x); smp_store_release(&y, 1);
> However, we *do* enforce ordering on any prior or subsequent accesses > for the code snippet above (the release and acquire combine to give a > full barrier), which makes these primitives well suited to things like > message passing.
If I understand your example correctly, neither x86 nor Power implement a full barrier in this case. For example:
P0 WRITE_ONCE(a, 1); smp_store_release(b, 1); r1 = smp_load_acquire(c); r2 = READ_ONCE(d);
P1 WRITE_ONCE(d, 1); smp_mb(); r3 = READ_ONCE(a);
Both x86 and Power can reorder P0 as follows:
P0 r1 = smp_load_acquire(c); r2 = READ_ONCE(d); WRITE_ONCE(a, 1); smp_store_release(b, 1);
Which clearly shows that the non-SC outcome r2 == 0 && r3 == 0 is allowed.
Or am I missing your point here?
Thanx, Paul
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