Messages in this thread | | | From | 平松雅巳 / HIRAMATU,MASAMI <> | Subject | RE: [PATCH 1/4] perf tools: Add a test for decoding of new x86 instructions | Date | Tue, 1 Sep 2015 00:18:03 +0000 |
| |
> From: Adrian Hunter [mailto:adrian.hunter@intel.com] > > Add a new test titled: > > Test x86 instruction decoder - new instructions > > The purpose of this test is to check the instruction decoder > after new instructions have been added. Initially, MPX > instructions are tested which are already supported, but the > definitions in x86-opcode-map.txt will be tweaked in a > subsequent patch, after which this test can be run to verify > those changes.
Hmm, btw, why should this test in perf? It seems that we need this test in kselftest or build-time selftest. I prefer to put this in arch/x86/tools/ or lib/. What would you think ?
Thanks,
> > The data for the test comes from assembly language instructions > in insn-x86-dat-src.c which is converted into bytes by the scripts > gen-insn-x86-dat.sh and gen-insn-x86-dat.awk, and included > into the test program insn-x86.c as insn-x86-dat-32.c and > insn-x86-dat-64.c. The conversion is not done as part of the > perf tools build because the test data must be under (git) > change control in order for the test to be repeatably-correct. > Also it may require a recent version of binutils. > > Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> > --- > tools/perf/tests/Build | 3 + > tools/perf/tests/builtin-test.c | 8 + > tools/perf/tests/gen-insn-x86-dat.awk | 75 ++++++ > tools/perf/tests/gen-insn-x86-dat.sh | 43 ++++ > tools/perf/tests/insn-x86-dat-32.c | 324 ++++++++++++++++++++++++++ > tools/perf/tests/insn-x86-dat-64.c | 340 +++++++++++++++++++++++++++ > tools/perf/tests/insn-x86-dat-src.c | 416 ++++++++++++++++++++++++++++++++++ > tools/perf/tests/insn-x86.c | 180 +++++++++++++++ > tools/perf/tests/tests.h | 1 + > 9 files changed, 1390 insertions(+) > create mode 100644 tools/perf/tests/gen-insn-x86-dat.awk > create mode 100755 tools/perf/tests/gen-insn-x86-dat.sh > create mode 100644 tools/perf/tests/insn-x86-dat-32.c > create mode 100644 tools/perf/tests/insn-x86-dat-64.c > create mode 100644 tools/perf/tests/insn-x86-dat-src.c > create mode 100644 tools/perf/tests/insn-x86.c > > diff --git a/tools/perf/tests/Build b/tools/perf/tests/Build > index c1518bdd0f1b..51fb737f82fc 100644 > --- a/tools/perf/tests/Build > +++ b/tools/perf/tests/Build > @@ -35,6 +35,9 @@ perf-y += thread-map.o > perf-y += llvm.o > > perf-$(CONFIG_X86) += perf-time-to-tsc.o > +ifdef CONFIG_AUXTRACE > +perf-$(CONFIG_X86) += insn-x86.o > +endif > > ifeq ($(ARCH),$(filter $(ARCH),x86 arm arm64)) > perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o > diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c > index 136cd934be66..69a77f71d594 100644 > --- a/tools/perf/tests/builtin-test.c > +++ b/tools/perf/tests/builtin-test.c > @@ -178,6 +178,14 @@ static struct test { > .desc = "Test LLVM searching and compiling", > .func = test__llvm, > }, > +#ifdef HAVE_AUXTRACE_SUPPORT > +#if defined(__x86_64__) || defined(__i386__) > + { > + .desc = "Test x86 instruction decoder - new instructions", > + .func = test__insn_x86, > + }, > +#endif > +#endif > { > .func = NULL, > }, > diff --git a/tools/perf/tests/gen-insn-x86-dat.awk b/tools/perf/tests/gen-insn-x86-dat.awk > new file mode 100644 > index 000000000000..a21454835cd4 > --- /dev/null > +++ b/tools/perf/tests/gen-insn-x86-dat.awk > @@ -0,0 +1,75 @@ > +#!/bin/awk -f > +# gen-insn-x86-dat.awk: script to convert data for the insn-x86 test > +# Copyright (c) 2015, Intel Corporation. > +# > +# This program is free software; you can redistribute it and/or modify it > +# under the terms and conditions of the GNU General Public License, > +# version 2, as published by the Free Software Foundation. > +# > +# This program is distributed in the hope it will be useful, but WITHOUT > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > +# more details. > + > +BEGIN { > + print "/*" > + print " * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk" > + print " * from insn-x86-dat-src.c for inclusion by insn-x86.c" > + print " * Do not change this code." > + print "*/\n" > + op = "" > + branch = "" > + rel = 0 > + going = 0 > +} > + > +/ Start here / { > + going = 1 > +} > + > +/ Stop here / { > + going = 0 > +} > + > +/^\s*[0-9a-fA-F]+\:/ { > + if (going) { > + colon_pos = index($0, ":") > + useful_line = substr($0, colon_pos + 1) > + first_pos = match(useful_line, "[0-9a-fA-F]") > + useful_line = substr(useful_line, first_pos) > + gsub("\t", "\\t", useful_line) > + printf "{{" > + len = 0 > + for (i = 2; i <= NF; i++) { > + if (match($i, "^[0-9a-fA-F][0-9a-fA-F]$")) { > + printf "0x%s, ", $i > + len += 1 > + } else { > + break > + } > + } > + printf "}, %d, %s, \"%s\", \"%s\",", len, rel, op, branch > + printf "\n\"%s\",},\n", useful_line > + op = "" > + branch = "" > + rel = 0 > + } > +} > + > +/ Expecting: / { > + expecting_str = " Expecting: " > + expecting_len = length(expecting_str) > + expecting_pos = index($0, expecting_str) > + useful_line = substr($0, expecting_pos + expecting_len) > + for (i = 1; i <= NF; i++) { > + if ($i == "Expecting:") { > + i++ > + op = $i > + i++ > + branch = $i > + i++ > + rel = $i > + break > + } > + } > +} > diff --git a/tools/perf/tests/gen-insn-x86-dat.sh b/tools/perf/tests/gen-insn-x86-dat.sh > new file mode 100755 > index 000000000000..2d4ef94cff98 > --- /dev/null > +++ b/tools/perf/tests/gen-insn-x86-dat.sh > @@ -0,0 +1,43 @@ > +#!/bin/sh > +# gen-insn-x86-dat: generate data for the insn-x86 test > +# Copyright (c) 2015, Intel Corporation. > +# > +# This program is free software; you can redistribute it and/or modify it > +# under the terms and conditions of the GNU General Public License, > +# version 2, as published by the Free Software Foundation. > +# > +# This program is distributed in the hope it will be useful, but WITHOUT > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > +# more details. > + > +set -e > + > +if [ "$(uname -m)" != "x86_64" ]; then > + echo "ERROR: This script only works on x86_64" > + exit 1 > +fi > + > +cd $(dirname $0) > + > +trap 'echo "Might need a more recent version of binutils"' EXIT > + > +echo "Compiling insn-x86-dat-src.c to 64-bit object" > + > +gcc -g -c insn-x86-dat-src.c > + > +objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-64.c > + > +rm -f insn-x86-dat-src.o > + > +echo "Compiling insn-x86-dat-src.c to 32-bit object" > + > +gcc -g -c -m32 insn-x86-dat-src.c > + > +objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-32.c > + > +rm -f insn-x86-dat-src.o > + > +trap - EXIT > + > +echo "Done (use git diff to see the changes)" > diff --git a/tools/perf/tests/insn-x86-dat-32.c b/tools/perf/tests/insn-x86-dat-32.c > new file mode 100644 > index 000000000000..6a38a34a5a49 > --- /dev/null > +++ b/tools/perf/tests/insn-x86-dat-32.c > @@ -0,0 +1,324 @@ > +/* > + * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk > + * from insn-x86-dat-src.c for inclusion by insn-x86.c > + * Do not change this code. > +*/ > + > +{{0x0f, 0x31, }, 2, 0, "", "", > +"0f 31 \trdtsc ",}, > +{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", > +"f3 0f 1b 00 \tbndmk (%eax),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1b 05 78 56 34 12 \tbndmk 0x12345678,%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", > +"f3 0f 1b 18 \tbndmk (%eax),%bnd3",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", > +"f3 0f 1b 04 01 \tbndmk (%ecx,%eax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%eax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", > +"f3 0f 1b 04 08 \tbndmk (%eax,%ecx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", > +"f3 0f 1b 04 c8 \tbndmk (%eax,%ecx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", > +"f3 0f 1b 40 12 \tbndmk 0x12(%eax),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", > +"f3 0f 1b 45 12 \tbndmk 0x12(%ebp),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 01 12 \tbndmk 0x12(%ecx,%eax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 05 12 \tbndmk 0x12(%ebp,%eax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 08 12 \tbndmk 0x12(%eax,%ecx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 c8 12 \tbndmk 0x12(%eax,%ecx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%eax),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%ebp),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%ecx,%eax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%ebp,%eax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%eax,%ecx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%eax,%ecx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", > +"f3 0f 1a 00 \tbndcl (%eax),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1a 05 78 56 34 12 \tbndcl 0x12345678,%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", > +"f3 0f 1a 18 \tbndcl (%eax),%bnd3",}, > +{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", > +"f3 0f 1a 04 01 \tbndcl (%ecx,%eax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", 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0x12345678(%eax,%ecx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1a 84 c8 78 56 34 12 \tbndcu 0x12345678(%eax,%ecx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "", > +"f2 0f 1a c0 \tbndcu %eax,%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", > +"f2 0f 1b 00 \tbndcn (%eax),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f2 0f 1b 05 78 56 34 12 \tbndcn 0x12345678,%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", > +"f2 0f 1b 18 \tbndcn (%eax),%bnd3",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", > +"f2 0f 1b 04 01 \tbndcn (%ecx,%eax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%eax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", > +"f2 0f 1b 04 08 \tbndcn (%eax,%ecx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", > +"f2 0f 1b 04 c8 \tbndcn (%eax,%ecx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", > +"f2 0f 1b 40 12 \tbndcn 0x12(%eax),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", > +"f2 0f 1b 45 12 \tbndcn 0x12(%ebp),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 01 12 \tbndcn 0x12(%ecx,%eax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 05 12 \tbndcn 0x12(%ebp,%eax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 08 12 \tbndcn 0x12(%eax,%ecx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 c8 12 \tbndcn 0x12(%eax,%ecx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%eax),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%ebp),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%ecx,%eax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%ebp,%eax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%eax,%ecx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%eax,%ecx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "", > +"f2 0f 1b c0 \tbndcn %eax,%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", > +"66 0f 1a 00 \tbndmov (%eax),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1a 05 78 56 34 12 \tbndmov 0x12345678,%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", > +"66 0f 1a 18 \tbndmov (%eax),%bnd3",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", > +"66 0f 1a 04 01 \tbndmov (%ecx,%eax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%eax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", > +"66 0f 1a 04 08 \tbndmov (%eax,%ecx,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", > +"66 0f 1a 04 c8 \tbndmov (%eax,%ecx,8),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", > +"66 0f 1a 40 12 \tbndmov 0x12(%eax),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", > +"66 0f 1a 45 12 \tbndmov 0x12(%ebp),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 01 12 \tbndmov 0x12(%ecx,%eax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 05 12 \tbndmov 0x12(%ebp,%eax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 08 12 \tbndmov 0x12(%eax,%ecx,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 c8 12 \tbndmov 0x12(%eax,%ecx,8),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%eax),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%ebp),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%ecx,%eax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%ebp,%eax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%eax,%ecx,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%eax,%ecx,8),%bnd0",}, > +{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", > +"66 0f 1b 00 \tbndmov %bnd0,(%eax)",}, > +{{0x66, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1b 05 78 56 34 12 \tbndmov %bnd0,0x12345678",}, > +{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", > +"66 0f 1b 18 \tbndmov %bnd3,(%eax)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", > +"66 0f 1b 04 01 \tbndmov %bnd0,(%ecx,%eax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%eax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", > +"66 0f 1b 04 08 \tbndmov %bnd0,(%eax,%ecx,1)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", > +"66 0f 1b 04 c8 \tbndmov %bnd0,(%eax,%ecx,8)",}, > +{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", > +"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%eax)",}, > +{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", > +"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%ebp)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 01 12 \tbndmov %bnd0,0x12(%ecx,%eax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%ebp,%eax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%eax,%ecx,1)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%eax,%ecx,8)",}, > +{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%eax)",}, > +{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%ebp)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%ecx,%eax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 05 78 56 34 12 \tbndmov %bnd0,0x12345678(%ebp,%eax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 08 78 56 34 12 \tbndmov %bnd0,0x12345678(%eax,%ecx,1)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 c8 78 56 34 12 \tbndmov %bnd0,0x12345678(%eax,%ecx,8)",}, > +{{0x66, 0x0f, 0x1a, 0xc8, }, 4, 0, "", "", > +"66 0f 1a c8 \tbndmov %bnd0,%bnd1",}, > +{{0x66, 0x0f, 0x1a, 0xc1, }, 4, 0, "", "", > +"66 0f 1a c1 \tbndmov %bnd1,%bnd0",}, > +{{0x0f, 0x1a, 0x00, }, 3, 0, "", "", > +"0f 1a 00 \tbndldx (%eax),%bnd0",}, > +{{0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1a 05 78 56 34 12 \tbndldx 0x12345678,%bnd0",}, > +{{0x0f, 0x1a, 0x18, }, 3, 0, "", "", > +"0f 1a 18 \tbndldx (%eax),%bnd3",}, > +{{0x0f, 0x1a, 0x04, 0x01, }, 4, 0, "", "", > +"0f 1a 04 01 \tbndldx (%ecx,%eax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 04 05 78 56 34 12 \tbndldx 0x12345678(,%eax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x04, 0x08, }, 4, 0, "", "", > +"0f 1a 04 08 \tbndldx (%eax,%ecx,1),%bnd0",}, > +{{0x0f, 0x1a, 0x40, 0x12, }, 4, 0, "", "", > +"0f 1a 40 12 \tbndldx 0x12(%eax),%bnd0",}, > +{{0x0f, 0x1a, 0x45, 0x12, }, 4, 0, "", "", > +"0f 1a 45 12 \tbndldx 0x12(%ebp),%bnd0",}, > +{{0x0f, 0x1a, 0x44, 0x01, 0x12, }, 5, 0, "", "", > +"0f 1a 44 01 12 \tbndldx 0x12(%ecx,%eax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x44, 0x05, 0x12, }, 5, 0, "", "", > +"0f 1a 44 05 12 \tbndldx 0x12(%ebp,%eax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x44, 0x08, 0x12, }, 5, 0, "", "", > +"0f 1a 44 08 12 \tbndldx 0x12(%eax,%ecx,1),%bnd0",}, > +{{0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1a 80 78 56 34 12 \tbndldx 0x12345678(%eax),%bnd0",}, > +{{0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1a 85 78 56 34 12 \tbndldx 0x12345678(%ebp),%bnd0",}, > +{{0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 84 01 78 56 34 12 \tbndldx 0x12345678(%ecx,%eax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 84 05 78 56 34 12 \tbndldx 0x12345678(%ebp,%eax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 84 08 78 56 34 12 \tbndldx 0x12345678(%eax,%ecx,1),%bnd0",}, > +{{0x0f, 0x1b, 0x00, }, 3, 0, "", "", > +"0f 1b 00 \tbndstx %bnd0,(%eax)",}, > +{{0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1b 05 78 56 34 12 \tbndstx %bnd0,0x12345678",}, > +{{0x0f, 0x1b, 0x18, }, 3, 0, "", "", > +"0f 1b 18 \tbndstx %bnd3,(%eax)",}, > +{{0x0f, 0x1b, 0x04, 0x01, }, 4, 0, "", "", > +"0f 1b 04 01 \tbndstx %bnd0,(%ecx,%eax,1)",}, > +{{0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 04 05 78 56 34 12 \tbndstx %bnd0,0x12345678(,%eax,1)",}, > +{{0x0f, 0x1b, 0x04, 0x08, }, 4, 0, "", "", > +"0f 1b 04 08 \tbndstx %bnd0,(%eax,%ecx,1)",}, > +{{0x0f, 0x1b, 0x40, 0x12, }, 4, 0, "", "", > +"0f 1b 40 12 \tbndstx %bnd0,0x12(%eax)",}, > +{{0x0f, 0x1b, 0x45, 0x12, }, 4, 0, "", "", > +"0f 1b 45 12 \tbndstx %bnd0,0x12(%ebp)",}, > +{{0x0f, 0x1b, 0x44, 0x01, 0x12, }, 5, 0, "", "", > +"0f 1b 44 01 12 \tbndstx %bnd0,0x12(%ecx,%eax,1)",}, > +{{0x0f, 0x1b, 0x44, 0x05, 0x12, }, 5, 0, "", "", > +"0f 1b 44 05 12 \tbndstx %bnd0,0x12(%ebp,%eax,1)",}, > +{{0x0f, 0x1b, 0x44, 0x08, 0x12, }, 5, 0, "", "", > +"0f 1b 44 08 12 \tbndstx %bnd0,0x12(%eax,%ecx,1)",}, > +{{0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1b 80 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax)",}, > +{{0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1b 85 78 56 34 12 \tbndstx %bnd0,0x12345678(%ebp)",}, > +{{0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 84 01 78 56 34 12 \tbndstx %bnd0,0x12345678(%ecx,%eax,1)",}, > +{{0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 84 05 78 56 34 12 \tbndstx %bnd0,0x12345678(%ebp,%eax,1)",}, > +{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",}, > +{{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional", > +"f2 e8 fc ff ff ff \tbnd call 3c3 <main+0x3c3>",}, > +{{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect", > +"f2 ff 10 \tbnd call *(%eax)",}, > +{{0xf2, 0xc3, }, 2, 0, "ret", "indirect", > +"f2 c3 \tbnd ret ",}, > +{{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", > +"f2 e9 fc ff ff ff \tbnd jmp 3ce <main+0x3ce>",}, > +{{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional", > +"f2 e9 fc ff ff ff \tbnd jmp 3d4 <main+0x3d4>",}, > +{{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect", > +"f2 ff 21 \tbnd jmp *(%ecx)",}, > +{{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional", > +"f2 0f 85 fc ff ff ff \tbnd jne 3de <main+0x3de>",}, > diff --git a/tools/perf/tests/insn-x86-dat-64.c b/tools/perf/tests/insn-x86-dat-64.c > new file mode 100644 > index 000000000000..01122421a776 > --- /dev/null > +++ b/tools/perf/tests/insn-x86-dat-64.c > @@ -0,0 +1,340 @@ > +/* > + * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk > + * from insn-x86-dat-src.c for inclusion by insn-x86.c > + * Do not change this code. > +*/ > + > +{{0x0f, 0x31, }, 2, 0, "", "", > +"0f 31 \trdtsc ",}, > +{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", > +"f3 0f 1b 00 \tbndmk (%rax),%bnd0",}, > +{{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", > +"f3 41 0f 1b 00 \tbndmk (%r8),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 04 25 78 56 34 12 \tbndmk 0x12345678,%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", > +"f3 0f 1b 18 \tbndmk (%rax),%bnd3",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", > +"f3 0f 1b 04 01 \tbndmk (%rcx,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", > +"f3 0f 1b 04 08 \tbndmk (%rax,%rcx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", > +"f3 0f 1b 04 c8 \tbndmk (%rax,%rcx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", > +"f3 0f 1b 40 12 \tbndmk 0x12(%rax),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", > +"f3 0f 1b 45 12 \tbndmk 0x12(%rbp),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 01 12 \tbndmk 0x12(%rcx,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 05 12 \tbndmk 0x12(%rbp,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 08 12 \tbndmk 0x12(%rax,%rcx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"f3 0f 1b 44 c8 12 \tbndmk 0x12(%rax,%rcx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%rax),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%rbp),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%rcx,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%rbp,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", > +"f3 0f 1a 00 \tbndcl (%rax),%bnd0",}, > +{{0xf3, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", > +"f3 41 0f 1a 00 \tbndcl (%r8),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1a 04 25 78 56 34 12 \tbndcl 0x12345678,%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", > +"f3 0f 1a 18 \tbndcl (%rax),%bnd3",}, > +{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", > +"f3 0f 1a 04 01 \tbndcl (%rcx,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", > +"f3 0f 1a 04 08 \tbndcl (%rax,%rcx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", > +"f3 0f 1a 04 c8 \tbndcl (%rax,%rcx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", > +"f3 0f 1a 40 12 \tbndcl 0x12(%rax),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", > +"f3 0f 1a 45 12 \tbndcl 0x12(%rbp),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"f3 0f 1a 44 01 12 \tbndcl 0x12(%rcx,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"f3 0f 1a 44 05 12 \tbndcl 0x12(%rbp,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"f3 0f 1a 44 08 12 \tbndcl 0x12(%rax,%rcx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"f3 0f 1a 44 c8 12 \tbndcl 0x12(%rax,%rcx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1a 80 78 56 34 12 \tbndcl 0x12345678(%rax),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f3 0f 1a 85 78 56 34 12 \tbndcl 0x12345678(%rbp),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1a 84 01 78 56 34 12 \tbndcl 0x12345678(%rcx,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1a 84 05 78 56 34 12 \tbndcl 0x12345678(%rbp,%rax,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1a 84 08 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,1),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f3 0f 1a 84 c8 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,8),%bnd0",}, > +{{0xf3, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "", > +"f3 0f 1a c0 \tbndcl %rax,%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", > +"f2 0f 1a 00 \tbndcu (%rax),%bnd0",}, > +{{0xf2, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", > +"f2 41 0f 1a 00 \tbndcu (%r8),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1a 04 25 78 56 34 12 \tbndcu 0x12345678,%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", > +"f2 0f 1a 18 \tbndcu (%rax),%bnd3",}, > +{{0xf2, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", > +"f2 0f 1a 04 01 \tbndcu (%rcx,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1a 04 05 78 56 34 12 \tbndcu 0x12345678(,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", > +"f2 0f 1a 04 08 \tbndcu (%rax,%rcx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", > +"f2 0f 1a 04 c8 \tbndcu (%rax,%rcx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", > +"f2 0f 1a 40 12 \tbndcu 0x12(%rax),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", > +"f2 0f 1a 45 12 \tbndcu 0x12(%rbp),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"f2 0f 1a 44 01 12 \tbndcu 0x12(%rcx,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"f2 0f 1a 44 05 12 \tbndcu 0x12(%rbp,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"f2 0f 1a 44 08 12 \tbndcu 0x12(%rax,%rcx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"f2 0f 1a 44 c8 12 \tbndcu 0x12(%rax,%rcx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f2 0f 1a 80 78 56 34 12 \tbndcu 0x12345678(%rax),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f2 0f 1a 85 78 56 34 12 \tbndcu 0x12345678(%rbp),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1a 84 01 78 56 34 12 \tbndcu 0x12345678(%rcx,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1a 84 05 78 56 34 12 \tbndcu 0x12345678(%rbp,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1a 84 08 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1a 84 c8 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "", > +"f2 0f 1a c0 \tbndcu %rax,%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", > +"f2 0f 1b 00 \tbndcn (%rax),%bnd0",}, > +{{0xf2, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", > +"f2 41 0f 1b 00 \tbndcn (%r8),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 04 25 78 56 34 12 \tbndcn 0x12345678,%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", > +"f2 0f 1b 18 \tbndcn (%rax),%bnd3",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", > +"f2 0f 1b 04 01 \tbndcn (%rcx,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", > +"f2 0f 1b 04 08 \tbndcn (%rax,%rcx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", > +"f2 0f 1b 04 c8 \tbndcn (%rax,%rcx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", > +"f2 0f 1b 40 12 \tbndcn 0x12(%rax),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", > +"f2 0f 1b 45 12 \tbndcn 0x12(%rbp),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 01 12 \tbndcn 0x12(%rcx,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 05 12 \tbndcn 0x12(%rbp,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 08 12 \tbndcn 0x12(%rax,%rcx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"f2 0f 1b 44 c8 12 \tbndcn 0x12(%rax,%rcx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%rax),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%rbp),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%rcx,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%rbp,%rax,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,1),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,8),%bnd0",}, > +{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "", > +"f2 0f 1b c0 \tbndcn %rax,%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", > +"66 0f 1a 00 \tbndmov (%rax),%bnd0",}, > +{{0x66, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", > +"66 41 0f 1a 00 \tbndmov (%r8),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 04 25 78 56 34 12 \tbndmov 0x12345678,%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", > +"66 0f 1a 18 \tbndmov (%rax),%bnd3",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", > +"66 0f 1a 04 01 \tbndmov (%rcx,%rax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%rax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", > +"66 0f 1a 04 08 \tbndmov (%rax,%rcx,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", > +"66 0f 1a 04 c8 \tbndmov (%rax,%rcx,8),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", > +"66 0f 1a 40 12 \tbndmov 0x12(%rax),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", > +"66 0f 1a 45 12 \tbndmov 0x12(%rbp),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 01 12 \tbndmov 0x12(%rcx,%rax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 05 12 \tbndmov 0x12(%rbp,%rax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 08 12 \tbndmov 0x12(%rax,%rcx,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"66 0f 1a 44 c8 12 \tbndmov 0x12(%rax,%rcx,8),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%rax),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%rbp),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%rcx,%rax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%rbp,%rax,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,1),%bnd0",}, > +{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,8),%bnd0",}, > +{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", > +"66 0f 1b 00 \tbndmov %bnd0,(%rax)",}, > +{{0x66, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", > +"66 41 0f 1b 00 \tbndmov %bnd0,(%r8)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 04 25 78 56 34 12 \tbndmov %bnd0,0x12345678",}, > +{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", > +"66 0f 1b 18 \tbndmov %bnd3,(%rax)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", > +"66 0f 1b 04 01 \tbndmov %bnd0,(%rcx,%rax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%rax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", > +"66 0f 1b 04 08 \tbndmov %bnd0,(%rax,%rcx,1)",}, > +{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", > +"66 0f 1b 04 c8 \tbndmov %bnd0,(%rax,%rcx,8)",}, > +{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", > +"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%rax)",}, > +{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", > +"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%rbp)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 01 12 \tbndmov %bnd0,0x12(%rcx,%rax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%rbp,%rax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%rax,%rcx,1)",}, > +{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", > +"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%rax,%rcx,8)",}, > +{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax)",}, > +{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%rcx,%rax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 05 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp,%rax,1)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 08 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,1)",}, > +{{0x66, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", > +"66 0f 1b 84 c8 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,8)",}, > +{{0x66, 0x0f, 0x1a, 0xc8, }, 4, 0, "", "", > +"66 0f 1a c8 \tbndmov %bnd0,%bnd1",}, > +{{0x66, 0x0f, 0x1a, 0xc1, }, 4, 0, "", "", > +"66 0f 1a c1 \tbndmov %bnd1,%bnd0",}, > +{{0x0f, 0x1a, 0x00, }, 3, 0, "", "", > +"0f 1a 00 \tbndldx (%rax),%bnd0",}, > +{{0x41, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", > +"41 0f 1a 00 \tbndldx (%r8),%bnd0",}, > +{{0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 04 25 78 56 34 12 \tbndldx 0x12345678,%bnd0",}, > +{{0x0f, 0x1a, 0x18, }, 3, 0, "", "", > +"0f 1a 18 \tbndldx (%rax),%bnd3",}, > +{{0x0f, 0x1a, 0x04, 0x01, }, 4, 0, "", "", > +"0f 1a 04 01 \tbndldx (%rcx,%rax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 04 05 78 56 34 12 \tbndldx 0x12345678(,%rax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x04, 0x08, }, 4, 0, "", "", > +"0f 1a 04 08 \tbndldx (%rax,%rcx,1),%bnd0",}, > +{{0x0f, 0x1a, 0x40, 0x12, }, 4, 0, "", "", > +"0f 1a 40 12 \tbndldx 0x12(%rax),%bnd0",}, > +{{0x0f, 0x1a, 0x45, 0x12, }, 4, 0, "", "", > +"0f 1a 45 12 \tbndldx 0x12(%rbp),%bnd0",}, > +{{0x0f, 0x1a, 0x44, 0x01, 0x12, }, 5, 0, "", "", > +"0f 1a 44 01 12 \tbndldx 0x12(%rcx,%rax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x44, 0x05, 0x12, }, 5, 0, "", "", > +"0f 1a 44 05 12 \tbndldx 0x12(%rbp,%rax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x44, 0x08, 0x12, }, 5, 0, "", "", > +"0f 1a 44 08 12 \tbndldx 0x12(%rax,%rcx,1),%bnd0",}, > +{{0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1a 80 78 56 34 12 \tbndldx 0x12345678(%rax),%bnd0",}, > +{{0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1a 85 78 56 34 12 \tbndldx 0x12345678(%rbp),%bnd0",}, > +{{0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 84 01 78 56 34 12 \tbndldx 0x12345678(%rcx,%rax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 84 05 78 56 34 12 \tbndldx 0x12345678(%rbp,%rax,1),%bnd0",}, > +{{0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1a 84 08 78 56 34 12 \tbndldx 0x12345678(%rax,%rcx,1),%bnd0",}, > +{{0x0f, 0x1b, 0x00, }, 3, 0, "", "", > +"0f 1b 00 \tbndstx %bnd0,(%rax)",}, > +{{0x41, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", > +"41 0f 1b 00 \tbndstx %bnd0,(%r8)",}, > +{{0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 04 25 78 56 34 12 \tbndstx %bnd0,0x12345678",}, > +{{0x0f, 0x1b, 0x18, }, 3, 0, "", "", > +"0f 1b 18 \tbndstx %bnd3,(%rax)",}, > +{{0x0f, 0x1b, 0x04, 0x01, }, 4, 0, "", "", > +"0f 1b 04 01 \tbndstx %bnd0,(%rcx,%rax,1)",}, > +{{0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 04 05 78 56 34 12 \tbndstx %bnd0,0x12345678(,%rax,1)",}, > +{{0x0f, 0x1b, 0x04, 0x08, }, 4, 0, "", "", > +"0f 1b 04 08 \tbndstx %bnd0,(%rax,%rcx,1)",}, > +{{0x0f, 0x1b, 0x40, 0x12, }, 4, 0, "", "", > +"0f 1b 40 12 \tbndstx %bnd0,0x12(%rax)",}, > +{{0x0f, 0x1b, 0x45, 0x12, }, 4, 0, "", "", > +"0f 1b 45 12 \tbndstx %bnd0,0x12(%rbp)",}, > +{{0x0f, 0x1b, 0x44, 0x01, 0x12, }, 5, 0, "", "", > +"0f 1b 44 01 12 \tbndstx %bnd0,0x12(%rcx,%rax,1)",}, > +{{0x0f, 0x1b, 0x44, 0x05, 0x12, }, 5, 0, "", "", > +"0f 1b 44 05 12 \tbndstx %bnd0,0x12(%rbp,%rax,1)",}, > +{{0x0f, 0x1b, 0x44, 0x08, 0x12, }, 5, 0, "", "", > +"0f 1b 44 08 12 \tbndstx %bnd0,0x12(%rax,%rcx,1)",}, > +{{0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1b 80 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax)",}, > +{{0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", > +"0f 1b 85 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp)",}, > +{{0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 84 01 78 56 34 12 \tbndstx %bnd0,0x12345678(%rcx,%rax,1)",}, > +{{0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 84 05 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp,%rax,1)",}, > +{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", > +"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",}, > +{{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional", > +"f2 e8 00 00 00 00 \tbnd callq 3f6 <main+0x3f6>",}, > +{{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect", > +"67 f2 ff 10 \tbnd callq *(%eax)",}, > +{{0xf2, 0xc3, }, 2, 0, "ret", "indirect", > +"f2 c3 \tbnd retq ",}, > +{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", > +"f2 e9 00 00 00 00 \tbnd jmpq 402 <main+0x402>",}, > +{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional", > +"f2 e9 00 00 00 00 \tbnd jmpq 408 <main+0x408>",}, > +{{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect", > +"67 f2 ff 21 \tbnd jmpq *(%ecx)",}, > +{{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional", > +"f2 0f 85 00 00 00 00 \tbnd jne 413 <main+0x413>",}, > diff --git a/tools/perf/tests/insn-x86-dat-src.c b/tools/perf/tests/insn-x86-dat-src.c > new file mode 100644 > index 000000000000..b506830f33a8 > --- /dev/null > +++ b/tools/perf/tests/insn-x86-dat-src.c > @@ -0,0 +1,416 @@ > +/* > + * This file contains instructions for testing by the test titled: > + * > + * "Test x86 instruction decoder - new instructions" > + * > + * Note that the 'Expecting' comment lines are consumed by the > + * gen-insn-x86-dat.awk script and have the format: > + * > + * Expecting: <op> <branch> <rel> > + * > + * If this file is changed, remember to run the gen-insn-x86-dat.sh > + * script and commit the result. > + * > + * Refer to insn-x86.c for more details. > + */ > + > +int main(void) > +{ > + /* Following line is a marker for the awk script - do not change */ > + asm volatile("rdtsc"); /* Start here */ > + > +#ifdef __x86_64__ > + > + /* bndmk m64, bnd */ > + > + asm volatile("bndmk (%rax), %bnd0"); > + asm volatile("bndmk (%r8), %bnd0"); > + asm volatile("bndmk (0x12345678), %bnd0"); > + asm volatile("bndmk (%rax), %bnd3"); > + asm volatile("bndmk (%rcx,%rax,1), %bnd0"); > + asm volatile("bndmk 0x12345678(,%rax,1), %bnd0"); > + asm volatile("bndmk (%rax,%rcx,1), %bnd0"); > + asm volatile("bndmk (%rax,%rcx,8), %bnd0"); > + asm volatile("bndmk 0x12(%rax), %bnd0"); > + asm volatile("bndmk 0x12(%rbp), %bnd0"); > + asm volatile("bndmk 0x12(%rcx,%rax,1), %bnd0"); > + asm volatile("bndmk 0x12(%rbp,%rax,1), %bnd0"); > + asm volatile("bndmk 0x12(%rax,%rcx,1), %bnd0"); > + asm volatile("bndmk 0x12(%rax,%rcx,8), %bnd0"); > + asm volatile("bndmk 0x12345678(%rax), %bnd0"); > + asm volatile("bndmk 0x12345678(%rbp), %bnd0"); > + asm volatile("bndmk 0x12345678(%rcx,%rax,1), %bnd0"); > + asm volatile("bndmk 0x12345678(%rbp,%rax,1), %bnd0"); > + asm volatile("bndmk 0x12345678(%rax,%rcx,1), %bnd0"); > + asm volatile("bndmk 0x12345678(%rax,%rcx,8), %bnd0"); > + > + /* bndcl r/m64, bnd */ > + > + asm volatile("bndcl (%rax), %bnd0"); > + asm volatile("bndcl (%r8), %bnd0"); > + asm volatile("bndcl (0x12345678), %bnd0"); > + asm volatile("bndcl (%rax), %bnd3"); > + asm volatile("bndcl (%rcx,%rax,1), %bnd0"); > + asm volatile("bndcl 0x12345678(,%rax,1), %bnd0"); > + asm volatile("bndcl (%rax,%rcx,1), %bnd0"); > + asm volatile("bndcl (%rax,%rcx,8), %bnd0"); > + asm volatile("bndcl 0x12(%rax), %bnd0"); > + asm volatile("bndcl 0x12(%rbp), %bnd0"); > + asm volatile("bndcl 0x12(%rcx,%rax,1), %bnd0"); > + asm volatile("bndcl 0x12(%rbp,%rax,1), %bnd0"); > + asm volatile("bndcl 0x12(%rax,%rcx,1), %bnd0"); > + asm volatile("bndcl 0x12(%rax,%rcx,8), %bnd0"); > + asm volatile("bndcl 0x12345678(%rax), %bnd0"); > + asm volatile("bndcl 0x12345678(%rbp), %bnd0"); > + asm volatile("bndcl 0x12345678(%rcx,%rax,1), %bnd0"); > + asm volatile("bndcl 0x12345678(%rbp,%rax,1), %bnd0"); > + asm volatile("bndcl 0x12345678(%rax,%rcx,1), %bnd0"); > + asm volatile("bndcl 0x12345678(%rax,%rcx,8), %bnd0"); > + asm volatile("bndcl %rax, %bnd0"); > + > + /* bndcu r/m64, bnd */ > + > + asm volatile("bndcu (%rax), %bnd0"); > + asm volatile("bndcu (%r8), %bnd0"); > + asm volatile("bndcu (0x12345678), %bnd0"); > + asm volatile("bndcu (%rax), %bnd3"); > + asm volatile("bndcu (%rcx,%rax,1), %bnd0"); > + asm volatile("bndcu 0x12345678(,%rax,1), %bnd0"); > + asm volatile("bndcu (%rax,%rcx,1), %bnd0"); > + asm volatile("bndcu (%rax,%rcx,8), %bnd0"); > + asm volatile("bndcu 0x12(%rax), %bnd0"); > + asm volatile("bndcu 0x12(%rbp), %bnd0"); > + asm volatile("bndcu 0x12(%rcx,%rax,1), %bnd0"); > + asm volatile("bndcu 0x12(%rbp,%rax,1), %bnd0"); > + asm volatile("bndcu 0x12(%rax,%rcx,1), %bnd0"); > + asm volatile("bndcu 0x12(%rax,%rcx,8), %bnd0"); > + asm volatile("bndcu 0x12345678(%rax), %bnd0"); > + asm volatile("bndcu 0x12345678(%rbp), %bnd0"); > + asm volatile("bndcu 0x12345678(%rcx,%rax,1), %bnd0"); > + asm volatile("bndcu 0x12345678(%rbp,%rax,1), %bnd0"); > + asm volatile("bndcu 0x12345678(%rax,%rcx,1), %bnd0"); > + asm volatile("bndcu 0x12345678(%rax,%rcx,8), %bnd0"); > + asm volatile("bndcu %rax, %bnd0"); > + > + /* bndcn r/m64, bnd */ > + > + asm volatile("bndcn (%rax), %bnd0"); > + asm volatile("bndcn (%r8), %bnd0"); > + asm volatile("bndcn (0x12345678), %bnd0"); > + asm volatile("bndcn (%rax), %bnd3"); > + asm volatile("bndcn (%rcx,%rax,1), %bnd0"); > + asm volatile("bndcn 0x12345678(,%rax,1), %bnd0"); > + asm volatile("bndcn (%rax,%rcx,1), %bnd0"); > + asm volatile("bndcn (%rax,%rcx,8), %bnd0"); > + asm volatile("bndcn 0x12(%rax), %bnd0"); > + asm volatile("bndcn 0x12(%rbp), %bnd0"); > + asm volatile("bndcn 0x12(%rcx,%rax,1), %bnd0"); > + asm volatile("bndcn 0x12(%rbp,%rax,1), %bnd0"); > + asm volatile("bndcn 0x12(%rax,%rcx,1), %bnd0"); > + asm volatile("bndcn 0x12(%rax,%rcx,8), %bnd0"); > + asm volatile("bndcn 0x12345678(%rax), %bnd0"); > + asm volatile("bndcn 0x12345678(%rbp), %bnd0"); > + asm volatile("bndcn 0x12345678(%rcx,%rax,1), %bnd0"); > + asm volatile("bndcn 0x12345678(%rbp,%rax,1), %bnd0"); > + asm volatile("bndcn 0x12345678(%rax,%rcx,1), %bnd0"); > + asm volatile("bndcn 0x12345678(%rax,%rcx,8), %bnd0"); > + asm volatile("bndcn %rax, %bnd0"); > + > + /* bndmov m128, bnd */ > + > + asm volatile("bndmov (%rax), %bnd0"); > + asm volatile("bndmov (%r8), %bnd0"); > + asm volatile("bndmov (0x12345678), %bnd0"); > + asm volatile("bndmov (%rax), %bnd3"); > + asm volatile("bndmov (%rcx,%rax,1), %bnd0"); > + asm volatile("bndmov 0x12345678(,%rax,1), %bnd0"); > + asm volatile("bndmov (%rax,%rcx,1), %bnd0"); > + asm volatile("bndmov (%rax,%rcx,8), %bnd0"); > + asm volatile("bndmov 0x12(%rax), %bnd0"); > + asm volatile("bndmov 0x12(%rbp), %bnd0"); > + asm volatile("bndmov 0x12(%rcx,%rax,1), %bnd0"); > + asm volatile("bndmov 0x12(%rbp,%rax,1), %bnd0"); > + asm volatile("bndmov 0x12(%rax,%rcx,1), %bnd0"); > + asm volatile("bndmov 0x12(%rax,%rcx,8), %bnd0"); > + asm volatile("bndmov 0x12345678(%rax), %bnd0"); > + asm volatile("bndmov 0x12345678(%rbp), %bnd0"); > + asm volatile("bndmov 0x12345678(%rcx,%rax,1), %bnd0"); > + asm volatile("bndmov 0x12345678(%rbp,%rax,1), %bnd0"); > + asm volatile("bndmov 0x12345678(%rax,%rcx,1), %bnd0"); > + asm volatile("bndmov 0x12345678(%rax,%rcx,8), %bnd0"); > + > + /* bndmov bnd, m128 */ > + > + asm volatile("bndmov %bnd0, (%rax)"); > + asm volatile("bndmov %bnd0, (%r8)"); > + asm volatile("bndmov %bnd0, (0x12345678)"); > + asm volatile("bndmov %bnd3, (%rax)"); > + asm volatile("bndmov %bnd0, (%rcx,%rax,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(,%rax,1)"); > + asm volatile("bndmov %bnd0, (%rax,%rcx,1)"); > + asm volatile("bndmov %bnd0, (%rax,%rcx,8)"); > + asm volatile("bndmov %bnd0, 0x12(%rax)"); > + asm volatile("bndmov %bnd0, 0x12(%rbp)"); > + asm volatile("bndmov %bnd0, 0x12(%rcx,%rax,1)"); > + asm volatile("bndmov %bnd0, 0x12(%rbp,%rax,1)"); > + asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,1)"); > + asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,8)"); > + asm volatile("bndmov %bnd0, 0x12345678(%rax)"); > + asm volatile("bndmov %bnd0, 0x12345678(%rbp)"); > + asm volatile("bndmov %bnd0, 0x12345678(%rcx,%rax,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(%rbp,%rax,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,8)"); > + > + /* bndmov bnd2, bnd1 */ > + > + asm volatile("bndmov %bnd0, %bnd1"); > + asm volatile("bndmov %bnd1, %bnd0"); > + > + /* bndldx mib, bnd */ > + > + asm volatile("bndldx (%rax), %bnd0"); > + asm volatile("bndldx (%r8), %bnd0"); > + asm volatile("bndldx (0x12345678), %bnd0"); > + asm volatile("bndldx (%rax), %bnd3"); > + asm volatile("bndldx (%rcx,%rax,1), %bnd0"); > + asm volatile("bndldx 0x12345678(,%rax,1), %bnd0"); > + asm volatile("bndldx (%rax,%rcx,1), %bnd0"); > + asm volatile("bndldx 0x12(%rax), %bnd0"); > + asm volatile("bndldx 0x12(%rbp), %bnd0"); > + asm volatile("bndldx 0x12(%rcx,%rax,1), %bnd0"); > + asm volatile("bndldx 0x12(%rbp,%rax,1), %bnd0"); > + asm volatile("bndldx 0x12(%rax,%rcx,1), %bnd0"); > + asm volatile("bndldx 0x12345678(%rax), %bnd0"); > + asm volatile("bndldx 0x12345678(%rbp), %bnd0"); > + asm volatile("bndldx 0x12345678(%rcx,%rax,1), %bnd0"); > + asm volatile("bndldx 0x12345678(%rbp,%rax,1), %bnd0"); > + asm volatile("bndldx 0x12345678(%rax,%rcx,1), %bnd0"); > + > + /* bndstx bnd, mib */ > + > + asm volatile("bndstx %bnd0, (%rax)"); > + asm volatile("bndstx %bnd0, (%r8)"); > + asm volatile("bndstx %bnd0, (0x12345678)"); > + asm volatile("bndstx %bnd3, (%rax)"); > + asm volatile("bndstx %bnd0, (%rcx,%rax,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(,%rax,1)"); > + asm volatile("bndstx %bnd0, (%rax,%rcx,1)"); > + asm volatile("bndstx %bnd0, 0x12(%rax)"); > + asm volatile("bndstx %bnd0, 0x12(%rbp)"); > + asm volatile("bndstx %bnd0, 0x12(%rcx,%rax,1)"); > + asm volatile("bndstx %bnd0, 0x12(%rbp,%rax,1)"); > + asm volatile("bndstx %bnd0, 0x12(%rax,%rcx,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(%rax)"); > + asm volatile("bndstx %bnd0, 0x12345678(%rbp)"); > + asm volatile("bndstx %bnd0, 0x12345678(%rcx,%rax,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(%rbp,%rax,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(%rax,%rcx,1)"); > + > + /* bnd prefix on call, ret, jmp and all jcc */ > + > + asm volatile("bnd call label1"); /* Expecting: call unconditional 0 */ > + asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */ > + asm volatile("bnd ret"); /* Expecting: ret indirect 0 */ > + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */ > + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */ > + asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */ > + asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0 */ > + > +#else /* #ifdef __x86_64__ */ > + > + /* bndmk m32, bnd */ > + > + asm volatile("bndmk (%eax), %bnd0"); > + asm volatile("bndmk (0x12345678), %bnd0"); > + asm volatile("bndmk (%eax), %bnd3"); > + asm volatile("bndmk (%ecx,%eax,1), %bnd0"); > + asm volatile("bndmk 0x12345678(,%eax,1), %bnd0"); > + asm volatile("bndmk (%eax,%ecx,1), %bnd0"); > + asm volatile("bndmk (%eax,%ecx,8), %bnd0"); > + asm volatile("bndmk 0x12(%eax), %bnd0"); > + asm volatile("bndmk 0x12(%ebp), %bnd0"); > + asm volatile("bndmk 0x12(%ecx,%eax,1), %bnd0"); > + asm volatile("bndmk 0x12(%ebp,%eax,1), %bnd0"); > + asm volatile("bndmk 0x12(%eax,%ecx,1), %bnd0"); > + asm volatile("bndmk 0x12(%eax,%ecx,8), %bnd0"); > + asm volatile("bndmk 0x12345678(%eax), %bnd0"); > + asm volatile("bndmk 0x12345678(%ebp), %bnd0"); > + asm volatile("bndmk 0x12345678(%ecx,%eax,1), %bnd0"); > + asm volatile("bndmk 0x12345678(%ebp,%eax,1), %bnd0"); > + asm volatile("bndmk 0x12345678(%eax,%ecx,1), %bnd0"); > + asm volatile("bndmk 0x12345678(%eax,%ecx,8), %bnd0"); > + > + /* bndcl r/m32, bnd */ > + > + asm volatile("bndcl (%eax), %bnd0"); > + asm volatile("bndcl (0x12345678), %bnd0"); > + asm volatile("bndcl (%eax), %bnd3"); > + asm volatile("bndcl (%ecx,%eax,1), %bnd0"); > + asm volatile("bndcl 0x12345678(,%eax,1), %bnd0"); > + asm volatile("bndcl (%eax,%ecx,1), %bnd0"); > + asm volatile("bndcl (%eax,%ecx,8), %bnd0"); > + asm volatile("bndcl 0x12(%eax), %bnd0"); > + asm volatile("bndcl 0x12(%ebp), %bnd0"); > + asm volatile("bndcl 0x12(%ecx,%eax,1), %bnd0"); > + asm volatile("bndcl 0x12(%ebp,%eax,1), %bnd0"); > + asm volatile("bndcl 0x12(%eax,%ecx,1), %bnd0"); > + asm volatile("bndcl 0x12(%eax,%ecx,8), %bnd0"); > + asm volatile("bndcl 0x12345678(%eax), %bnd0"); > + asm volatile("bndcl 0x12345678(%ebp), %bnd0"); > + asm volatile("bndcl 0x12345678(%ecx,%eax,1), %bnd0"); > + asm volatile("bndcl 0x12345678(%ebp,%eax,1), %bnd0"); > + asm volatile("bndcl 0x12345678(%eax,%ecx,1), %bnd0"); > + asm volatile("bndcl 0x12345678(%eax,%ecx,8), %bnd0"); > + asm volatile("bndcl %eax, %bnd0"); > + > + /* bndcu r/m32, bnd */ > + > + asm volatile("bndcu (%eax), %bnd0"); > + asm volatile("bndcu (0x12345678), %bnd0"); > + asm volatile("bndcu (%eax), %bnd3"); > + asm volatile("bndcu (%ecx,%eax,1), %bnd0"); > + asm volatile("bndcu 0x12345678(,%eax,1), %bnd0"); > + asm volatile("bndcu (%eax,%ecx,1), %bnd0"); > + asm volatile("bndcu (%eax,%ecx,8), %bnd0"); > + asm volatile("bndcu 0x12(%eax), %bnd0"); > + asm volatile("bndcu 0x12(%ebp), %bnd0"); > + asm volatile("bndcu 0x12(%ecx,%eax,1), %bnd0"); > + asm volatile("bndcu 0x12(%ebp,%eax,1), %bnd0"); > + asm volatile("bndcu 0x12(%eax,%ecx,1), %bnd0"); > + asm volatile("bndcu 0x12(%eax,%ecx,8), %bnd0"); > + asm volatile("bndcu 0x12345678(%eax), %bnd0"); > + asm volatile("bndcu 0x12345678(%ebp), %bnd0"); > + asm volatile("bndcu 0x12345678(%ecx,%eax,1), %bnd0"); > + asm volatile("bndcu 0x12345678(%ebp,%eax,1), %bnd0"); > + asm volatile("bndcu 0x12345678(%eax,%ecx,1), %bnd0"); > + asm volatile("bndcu 0x12345678(%eax,%ecx,8), %bnd0"); > + asm volatile("bndcu %eax, %bnd0"); > + > + /* bndcn r/m32, bnd */ > + > + asm volatile("bndcn (%eax), %bnd0"); > + asm volatile("bndcn (0x12345678), %bnd0"); > + asm volatile("bndcn (%eax), %bnd3"); > + asm volatile("bndcn (%ecx,%eax,1), %bnd0"); > + asm volatile("bndcn 0x12345678(,%eax,1), %bnd0"); > + asm volatile("bndcn (%eax,%ecx,1), %bnd0"); > + asm volatile("bndcn (%eax,%ecx,8), %bnd0"); > + asm volatile("bndcn 0x12(%eax), %bnd0"); > + asm volatile("bndcn 0x12(%ebp), %bnd0"); > + asm volatile("bndcn 0x12(%ecx,%eax,1), %bnd0"); > + asm volatile("bndcn 0x12(%ebp,%eax,1), %bnd0"); > + asm volatile("bndcn 0x12(%eax,%ecx,1), %bnd0"); > + asm volatile("bndcn 0x12(%eax,%ecx,8), %bnd0"); > + asm volatile("bndcn 0x12345678(%eax), %bnd0"); > + asm volatile("bndcn 0x12345678(%ebp), %bnd0"); > + asm volatile("bndcn 0x12345678(%ecx,%eax,1), %bnd0"); > + asm volatile("bndcn 0x12345678(%ebp,%eax,1), %bnd0"); > + asm volatile("bndcn 0x12345678(%eax,%ecx,1), %bnd0"); > + asm volatile("bndcn 0x12345678(%eax,%ecx,8), %bnd0"); > + asm volatile("bndcn %eax, %bnd0"); > + > + /* bndmov m64, bnd */ > + > + asm volatile("bndmov (%eax), %bnd0"); > + asm volatile("bndmov (0x12345678), %bnd0"); > + asm volatile("bndmov (%eax), %bnd3"); > + asm volatile("bndmov (%ecx,%eax,1), %bnd0"); > + asm volatile("bndmov 0x12345678(,%eax,1), %bnd0"); > + asm volatile("bndmov (%eax,%ecx,1), %bnd0"); > + asm volatile("bndmov (%eax,%ecx,8), %bnd0"); > + asm volatile("bndmov 0x12(%eax), %bnd0"); > + asm volatile("bndmov 0x12(%ebp), %bnd0"); > + asm volatile("bndmov 0x12(%ecx,%eax,1), %bnd0"); > + asm volatile("bndmov 0x12(%ebp,%eax,1), %bnd0"); > + asm volatile("bndmov 0x12(%eax,%ecx,1), %bnd0"); > + asm volatile("bndmov 0x12(%eax,%ecx,8), %bnd0"); > + asm volatile("bndmov 0x12345678(%eax), %bnd0"); > + asm volatile("bndmov 0x12345678(%ebp), %bnd0"); > + asm volatile("bndmov 0x12345678(%ecx,%eax,1), %bnd0"); > + asm volatile("bndmov 0x12345678(%ebp,%eax,1), %bnd0"); > + asm volatile("bndmov 0x12345678(%eax,%ecx,1), %bnd0"); > + asm volatile("bndmov 0x12345678(%eax,%ecx,8), %bnd0"); > + > + /* bndmov bnd, m64 */ > + > + asm volatile("bndmov %bnd0, (%eax)"); > + asm volatile("bndmov %bnd0, (0x12345678)"); > + asm volatile("bndmov %bnd3, (%eax)"); > + asm volatile("bndmov %bnd0, (%ecx,%eax,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(,%eax,1)"); > + asm volatile("bndmov %bnd0, (%eax,%ecx,1)"); > + asm volatile("bndmov %bnd0, (%eax,%ecx,8)"); > + asm volatile("bndmov %bnd0, 0x12(%eax)"); > + asm volatile("bndmov %bnd0, 0x12(%ebp)"); > + asm volatile("bndmov %bnd0, 0x12(%ecx,%eax,1)"); > + asm volatile("bndmov %bnd0, 0x12(%ebp,%eax,1)"); > + asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,1)"); > + asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,8)"); > + asm volatile("bndmov %bnd0, 0x12345678(%eax)"); > + asm volatile("bndmov %bnd0, 0x12345678(%ebp)"); > + asm volatile("bndmov %bnd0, 0x12345678(%ecx,%eax,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(%ebp,%eax,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,1)"); > + asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,8)"); > + > + /* bndmov bnd2, bnd1 */ > + > + asm volatile("bndmov %bnd0, %bnd1"); > + asm volatile("bndmov %bnd1, %bnd0"); > + > + /* bndldx mib, bnd */ > + > + asm volatile("bndldx (%eax), %bnd0"); > + asm volatile("bndldx (0x12345678), %bnd0"); > + asm volatile("bndldx (%eax), %bnd3"); > + asm volatile("bndldx (%ecx,%eax,1), %bnd0"); > + asm volatile("bndldx 0x12345678(,%eax,1), %bnd0"); > + asm volatile("bndldx (%eax,%ecx,1), %bnd0"); > + asm volatile("bndldx 0x12(%eax), %bnd0"); > + asm volatile("bndldx 0x12(%ebp), %bnd0"); > + asm volatile("bndldx 0x12(%ecx,%eax,1), %bnd0"); > + asm volatile("bndldx 0x12(%ebp,%eax,1), %bnd0"); > + asm volatile("bndldx 0x12(%eax,%ecx,1), %bnd0"); > + asm volatile("bndldx 0x12345678(%eax), %bnd0"); > + asm volatile("bndldx 0x12345678(%ebp), %bnd0"); > + asm volatile("bndldx 0x12345678(%ecx,%eax,1), %bnd0"); > + asm volatile("bndldx 0x12345678(%ebp,%eax,1), %bnd0"); > + asm volatile("bndldx 0x12345678(%eax,%ecx,1), %bnd0"); > + > + /* bndstx bnd, mib */ > + > + asm volatile("bndstx %bnd0, (%eax)"); > + asm volatile("bndstx %bnd0, (0x12345678)"); > + asm volatile("bndstx %bnd3, (%eax)"); > + asm volatile("bndstx %bnd0, (%ecx,%eax,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(,%eax,1)"); > + asm volatile("bndstx %bnd0, (%eax,%ecx,1)"); > + asm volatile("bndstx %bnd0, 0x12(%eax)"); > + asm volatile("bndstx %bnd0, 0x12(%ebp)"); > + asm volatile("bndstx %bnd0, 0x12(%ecx,%eax,1)"); > + asm volatile("bndstx %bnd0, 0x12(%ebp,%eax,1)"); > + asm volatile("bndstx %bnd0, 0x12(%eax,%ecx,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(%eax)"); > + asm volatile("bndstx %bnd0, 0x12345678(%ebp)"); > + asm volatile("bndstx %bnd0, 0x12345678(%ecx,%eax,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(%ebp,%eax,1)"); > + asm volatile("bndstx %bnd0, 0x12345678(%eax,%ecx,1)"); > + > + /* bnd prefix on call, ret, jmp and all jcc */ > + > + asm volatile("bnd call label1"); /* Expecting: call unconditional 0xfffffffc */ > + asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */ > + asm volatile("bnd ret"); /* Expecting: ret indirect 0 */ > + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */ > + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */ > + asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */ > + asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0xfffffffc */ > + > +#endif /* #ifndef __x86_64__ */ > + > + /* Following line is a marker for the awk script - do not change */ > + asm volatile("rdtsc"); /* Stop here */ > + > + return 0; > +} > diff --git a/tools/perf/tests/insn-x86.c b/tools/perf/tests/insn-x86.c > new file mode 100644 > index 000000000000..0e126a099874 > --- /dev/null > +++ b/tools/perf/tests/insn-x86.c > @@ -0,0 +1,180 @@ > +#include <linux/types.h> > + > +#include "debug.h" > +#include "tests.h" > + > +#include "intel-pt-decoder/insn.h" > +#include "intel-pt-decoder/intel-pt-insn-decoder.h" > + > +struct test_data { > + u8 data[MAX_INSN_SIZE]; > + int expected_length; > + int expected_rel; > + const char *expected_op_str; > + const char *expected_branch_str; > + const char *asm_rep; > +}; > + > +struct test_data test_data_32[] = { > +#include "insn-x86-dat-32.c" > + {{0}, 0, 0, NULL, NULL, NULL}, > +}; > + > +struct test_data test_data_64[] = { > +#include "insn-x86-dat-64.c" > + {{0}, 0, 0, NULL, NULL, NULL}, > +}; > + > +static int get_op(const char *op_str) > +{ > + struct val_data { > + const char *name; > + int val; > + } vals[] = { > + {"other", INTEL_PT_OP_OTHER}, > + {"call", INTEL_PT_OP_CALL}, > + {"ret", INTEL_PT_OP_RET}, > + {"jcc", INTEL_PT_OP_JCC}, > + {"jmp", INTEL_PT_OP_JMP}, > + {"loop", INTEL_PT_OP_LOOP}, > + {"iret", INTEL_PT_OP_IRET}, > + {"int", INTEL_PT_OP_INT}, > + {"syscall", INTEL_PT_OP_SYSCALL}, > + {"sysret", INTEL_PT_OP_SYSRET}, > + {NULL, 0}, > + }; > + struct val_data *val; > + > + if (!op_str || !strlen(op_str)) > + return 0; > + > + for (val = vals; val->name; val++) { > + if (!strcmp(val->name, op_str)) > + return val->val; > + } > + > + pr_debug("Failed to get op\n"); > + > + return -1; > +} > + > +static int get_branch(const char *branch_str) > +{ > + struct val_data { > + const char *name; > + int val; > + } vals[] = { > + {"no_branch", INTEL_PT_BR_NO_BRANCH}, > + {"indirect", INTEL_PT_BR_INDIRECT}, > + {"conditional", INTEL_PT_BR_CONDITIONAL}, > + {"unconditional", INTEL_PT_BR_UNCONDITIONAL}, > + {NULL, 0}, > + }; > + struct val_data *val; > + > + if (!branch_str || !strlen(branch_str)) > + return 0; > + > + for (val = vals; val->name; val++) { > + if (!strcmp(val->name, branch_str)) > + return val->val; > + } > + > + pr_debug("Failed to get branch\n"); > + > + return -1; > +} > + > +static int test_data_item(struct test_data *dat, int x86_64) > +{ > + struct intel_pt_insn intel_pt_insn; > + struct insn insn; > + int op, branch; > + > + insn_init(&insn, dat->data, MAX_INSN_SIZE, x86_64); > + insn_get_length(&insn); > + > + if (!insn_complete(&insn)) { > + pr_debug("Failed to decode: %s\n", dat->asm_rep); > + return -1; > + } > + > + if (insn.length != dat->expected_length) { > + pr_debug("Failed to decode length (%d vs expected %d): %s\n", > + insn.length, dat->expected_length, dat->asm_rep); > + return -1; > + } > + > + op = get_op(dat->expected_op_str); > + branch = get_branch(dat->expected_branch_str); > + > + if (intel_pt_get_insn(dat->data, MAX_INSN_SIZE, x86_64, &intel_pt_insn)) { > + pr_debug("Intel PT failed to decode: %s\n", dat->asm_rep); > + return -1; > + } > + > + if ((int)intel_pt_insn.op != op) { > + pr_debug("Failed to decode 'op' value (%d vs expected %d): %s\n", > + intel_pt_insn.op, op, dat->asm_rep); > + return -1; > + } > + > + if ((int)intel_pt_insn.branch != branch) { > + pr_debug("Failed to decode 'branch' value (%d vs expected %d): %s\n", > + intel_pt_insn.branch, branch, dat->asm_rep); > + return -1; > + } > + > + if (intel_pt_insn.rel != dat->expected_rel) { > + pr_debug("Failed to decode 'rel' value (%#x vs expected %#x): %s\n", > + intel_pt_insn.rel, dat->expected_rel, dat->asm_rep); > + return -1; > + } > + > + pr_debug("Decoded ok: %s\n", dat->asm_rep); > + > + return 0; > +} > + > +static int test_data_set(struct test_data *dat_set, int x86_64) > +{ > + struct test_data *dat; > + int ret = 0; > + > + for (dat = dat_set; dat->expected_length; dat++) { > + if (test_data_item(dat, x86_64)) > + ret = -1; > + } > + > + return ret; > +} > + > +/** > + * test__insn_x86 - test x86 instruction decoder - new instructions. > + * > + * This function implements a test that decodes a selection of instructions and > + * checks the results. The Intel PT function that further categorizes > + * instructions (i.e. intel_pt_get_insn()) is also checked. > + * > + * The instructions are originally in insn-x86-dat-src.c which has been > + * processed by scripts gen-insn-x86-dat.sh and gen-insn-x86-dat.awk to produce > + * insn-x86-dat-32.c and insn-x86-dat-64.c which are included into this program. > + * i.e. to add new instructions to the test, edit insn-x86-dat-src.c, run the > + * gen-insn-x86-dat.sh script, make perf, and then run the test. > + * > + * If the test passes %0 is returned, otherwise %-1 is returned. Use the > + * verbose (-v) option to see all the instructions and whether or not they > + * decoded successfuly. > + */ > +int test__insn_x86(void) > +{ > + int ret = 0; > + > + if (test_data_set(test_data_32, 0)) > + ret = -1; > + > + if (test_data_set(test_data_64, 1)) > + ret = -1; > + > + return ret; > +} > diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h > index bf113a247987..4e2c5458269a 100644 > --- a/tools/perf/tests/tests.h > +++ b/tools/perf/tests/tests.h > @@ -63,6 +63,7 @@ int test__fdarray__add(void); > int test__kmod_path__parse(void); > int test__thread_map(void); > int test__llvm(void); > +int test__insn_x86(void); > > #if defined(__x86_64__) || defined(__i386__) || defined(__arm__) || defined(__aarch64__) > #ifdef HAVE_DWARF_UNWIND_SUPPORT > -- > 1.9.1
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