Messages in this thread | | | Date | Thu, 30 Jul 2015 10:54:13 -0700 (PDT) | From | Vikas Shivappa <> | Subject | Re: [PATCH 6/9] x86/intel_rdt: Add support for cache bit mask management |
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On Tue, 28 Jul 2015, Peter Zijlstra wrote:
> On Wed, Jul 01, 2015 at 03:21:07PM -0700, Vikas Shivappa wrote: >> +static int cbm_validate(struct intel_rdt *ir, unsigned long cbmvalue) >> +{ >> + struct cgroup_subsys_state *css; >> + struct intel_rdt *par, *c; >> + unsigned long *cbm_tmp; >> + int err = 0; >> + >> + if (!cbm_is_contiguous(cbmvalue)) { >> + pr_err("bitmask should have >= 1 bit and be contiguous\n"); >> + err = -EINVAL; >> + goto out_err; >> + } > >> +static struct cftype rdt_files[] = { >> + { >> + .name = "l3_cache_mask", >> + .seq_show = intel_cache_alloc_cbm_read, >> + .write_u64 = intel_cache_alloc_cbm_write, >> + .mode = 0666, > > So this file is world writable? How is the above pr_err() not a DoS ?
Will fix. the mode can be default and can remove pr_err Thanks, Vikas
> >> + }, >> + { } /* terminate */ >> +}; >
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