Messages in this thread | | | Date | Fri, 24 Jul 2015 14:41:13 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk |
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On 07/22, dinguyen@opensource.altera.com wrote: > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > index 80f924d..7d5db54 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/socfpga.dtsi > @@ -164,7 +164,7 @@ > dbg_base_clk: dbg_base_clk { > #clock-cells = <0>; > compatible = "altr,socfpga-perip-clk"; > - clocks = <&main_pll>; > + clocks = <&main_pll>, <&osc1>; > div-reg = <0xe8 0 9>; > reg = <0x50>; > };
We don't usually take changes in dts files. Can you split this off and take it through arm-soc?
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