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SubjectRe: [PATCH] Documentation: Minor changes to men-chameleon-bus.txt
On 07/21/15 07:16, Johannes Thumshirn wrote:
> Change men-chameleon-bus.txt according to the comments made by Randy Dunlap in
> https://lkml.org/lkml/2015/7/17/691.
>
> These are:
> * Some minor gramatical changes
> * Spelling fixes
> * Write the word "Chameleon" capitalized throughout the whole document
> * Explain MEN as MEN Mikro Elektronik GmbH.
>
> Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de>
> ---
> Documentation/men-chameleon-bus.txt | 39 +++++++++++++++++++------------------
> 1 file changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/Documentation/men-chameleon-bus.txt b/Documentation/men-chameleon-bus.txt
> index 6d7bdb5..39ed5ae 100644
> --- a/Documentation/men-chameleon-bus.txt
> +++ b/Documentation/men-chameleon-bus.txt
> @@ -43,40 +43,41 @@ Table of Contents
>
> 2 Architecture
> ===============
> - MCB is divided in 3 functional blocks:
> + MCB is divided into 3 functional blocks:
> - The MEN Chameleon Bus itself,
> - drivers for MCB Carrier Devices and
> - the parser for the Chameleon table.
>
> 2.1 MEN Chameleon Bus
> ----------------------
> - The MEN Chameleon Bus is an artificial bus system that attaches to an MEN
> - Chameleon FPGA device. These devices are multi-function devices implemented
> - in a single FPGA and usually attached via some sort of PCI or PCIe link. Each
> - FPGA contains a header section describing the content of the FPGA. The header
> - lists the device id, PCI BAR, offset from the beginning of the PCI BAR, size
> - in the FPGA, interrupt number and some other properties currently not handled
> - by the MCB implementation.
> + The MEN Chameleon Bus is an artificial bus system that attaches to an so

to a

> + called Chameleon FPGA device found on some Hardware produced my MEN Mikro

hardware

> + Elektronik GmbH. These devices are multi-function devices implemented in a
> + single FPGA and usually attached via some sort of PCI or PCIe link. Each
> + FPGA contains a header section describing the content of the FPGA. The
> + header lists the device id, PCI BAR, offset from the beginning of the PCI
> + BAR, size in the FPGA, interrupt number and some other properties currently
> + not handled by the MCB implementation.

Thanks for the update.

--
~Randy


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