Messages in this thread | | | Date | Mon, 13 Jul 2015 15:59:07 +0100 | From | Mark Brown <> | Subject | Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller |
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On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote: > On 09-07-15 14:44, Ranjit Waghmode wrote:
> >ZynqMP GQSPI controller supports stacked mode with following functionalities: > >1) The Generic Quad-SPI controller also supports two SPI flash memories > > in a shared bus arrangement to reduce IO pin count. > >2) Separate chip select lines > >3) Shared I/O lines > >4) This mode is targeted for increasing the flash memory and no performance > > improvement when compared with single.
> One could also model the stacked mode as having two distinct flash chips > with separate chip selects and shared lines.
Well, quite. I'm confused about how the above differs from a just a SPI controller with two chip selects which is perfectly standard. [unhandled content-type:application/pgp-signature] | |