lkml.org 
[lkml]   [2015]   [Jun]   [8]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    SubjectRe: [PATCH v4 6/8] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
    From
    Date
    On Mon, 2015-06-08 at 11:40 +0100, Sudeep Holla wrote:
    [...]
    > +
    > + scpi {
    > + compatible = "arm,scpi";
    > + mboxes = <&mailbox 1>;
    > + shmem = <&cpu_scp_hpri>;
    > +
    > + clocks {
    > + compatible = "arm,scpi-clocks";
    > +
    > + scpi_dvfs: scpi_clocks@0 {
    > + compatible = "arm,scpi-dvfs-clocks";
    > + #clock-cells = <1>;
    > + clock-indices = <0>, <1>, <2>;
    > + clock-output-names = "vbig", "vlittle", "vgpu";

    From where do the clock names derive? They look more like names for
    voltage domains rather than clocks. My (admittedly very old) Juno docs,
    have the clocks as ATLCLK, APLCLK and GPUCLK.

    > + };
    > + scpi_clk: scpi_clocks@3 {
    > + compatible = "arm,scpi-variable-clocks";
    > + #clock-cells = <1>;
    > + clock-indices = <3>, <4>;
    > + clock-output-names = "pxlclk0", "pxlclk1";

    Can we also have clock index 5, name 'i2s_clk', for used by audio?
    (I don't know what other clocks the SCP currently supports, but audio is
    one being currently used by the out-of-tree code).

    Also, I believe that both display outputs share the same clock, and so
    pxlclk0 and pxlclk1 can't be controlled independently. But I guess these
    device-tree entries are for the interface to the SCP firmware, not the
    hardware, and if that pretends the clocks are independent...

    --
    Tixy




    \
     
     \ /
      Last update: 2015-06-08 16:21    [W:3.717 / U:0.024 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site