Messages in this thread Patch in this message | | | From | Andi Kleen <> | Subject | [PATCH 2/3] x86, perf: Use 0x11 as extra reg test value | Date | Tue, 30 Jun 2015 16:33:24 -0700 |
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From: Andi Kleen <ak@linux.intel.com>
The next patch adds a new perf extra reg where 0x1ff is not a valid value. Use 0x11 instead.
Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 7c397e8..28b985c 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -3575,7 +3575,7 @@ __init int intel_pmu_init(void) */ if (x86_pmu.extra_regs) { for (er = x86_pmu.extra_regs; er->msr; er++) { - er->extra_msr_access = check_msr(er->msr, 0x1ffUL); + er->extra_msr_access = check_msr(er->msr, 0x11UL); /* Disable LBR select mapping */ if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) x86_pmu.lbr_sel_map = NULL; -- 2.4.2
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