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    Subject[PATCH 3.19.y-ckt 058/146] drm/radeon: fix VM_CONTEXT*_PAGE_TABLE_END_ADDR handling
    Date
    3.19.8-ckt2 -stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>

    commit 607d48063512707a414e346972e2210dc71ab491 upstream.

    The mapping range is inclusive between starting and ending addresses.

    Signed-off-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Kamal Mostafa <kamal@canonical.com>
    ---
    drivers/gpu/drm/radeon/cik.c | 4 ++--
    drivers/gpu/drm/radeon/evergreen.c | 2 +-
    drivers/gpu/drm/radeon/ni.c | 5 +++--
    drivers/gpu/drm/radeon/r600.c | 2 +-
    drivers/gpu/drm/radeon/rv770.c | 2 +-
    drivers/gpu/drm/radeon/si.c | 4 ++--
    6 files changed, 10 insertions(+), 9 deletions(-)

    diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
    index 53b9ac3..799a29f 100644
    --- a/drivers/gpu/drm/radeon/cik.c
    +++ b/drivers/gpu/drm/radeon/cik.c
    @@ -5764,7 +5764,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
    L2_CACHE_BIGK_FRAGMENT_SIZE(4));
    /* setup context0 */
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
    (u32)(rdev->dummy_page.addr >> 12));
    @@ -5779,7 +5779,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
    /* restore context1-15 */
    /* set vm size, must be a multiple of 4 */
    WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
    - WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
    + WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
    for (i = 1; i < 16; i++) {
    if (i < 8)
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
    diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
    index c674f63..d9f431d 100644
    --- a/drivers/gpu/drm/radeon/evergreen.c
    +++ b/drivers/gpu/drm/radeon/evergreen.c
    @@ -2456,7 +2456,7 @@ static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
    WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
    WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
    diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
    index 88b2c36..16f912a 100644
    --- a/drivers/gpu/drm/radeon/ni.c
    +++ b/drivers/gpu/drm/radeon/ni.c
    @@ -1250,7 +1250,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
    L2_CACHE_BIGK_FRAGMENT_SIZE(6));
    /* setup context0 */
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
    (u32)(rdev->dummy_page.addr >> 12));
    @@ -1269,7 +1269,8 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
    */
    for (i = 1; i < 8; i++) {
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
    + rdev->vm_manager.max_pfn - 1);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
    rdev->vm_manager.saved_table_addr[i]);
    }
    diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
    index 0e2cf2a..64ca89e 100644
    --- a/drivers/gpu/drm/radeon/r600.c
    +++ b/drivers/gpu/drm/radeon/r600.c
    @@ -1085,7 +1085,7 @@ static int r600_pcie_gart_enable(struct radeon_device *rdev)
    WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
    WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
    diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
    index 372016e..819c2c1 100644
    --- a/drivers/gpu/drm/radeon/rv770.c
    +++ b/drivers/gpu/drm/radeon/rv770.c
    @@ -920,7 +920,7 @@ static int rv770_pcie_gart_enable(struct radeon_device *rdev)
    WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
    WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
    diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
    index eed21db..2c8be31 100644
    --- a/drivers/gpu/drm/radeon/si.c
    +++ b/drivers/gpu/drm/radeon/si.c
    @@ -4270,7 +4270,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
    L2_CACHE_BIGK_FRAGMENT_SIZE(4));
    /* setup context0 */
    WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
    - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
    + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end >> 12) - 1);
    WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
    WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
    (u32)(rdev->dummy_page.addr >> 12));
    @@ -4285,7 +4285,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
    /* empty context1-15 */
    /* set vm size, must be a multiple of 4 */
    WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
    - WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
    + WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
    /* Assign the pt base to something valid for now; the pts used for
    * the VMs are determined by the application and setup and assigned
    * on the fly in the vm part of radeon_gart.c
    --
    1.9.1


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