lkml.org 
[lkml]   [2015]   [Jun]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: [PATCH 10/10] x86/intel_rdt: Intel haswell Cache Allocation enumeration
    On Fri, Jun 12, 2015 at 11:17:17AM -0700, Vikas Shivappa wrote:
    > + /*
    > + * Probe test for Haswell CPUs.
    > + */
    > + if (c->x86 == 0x6 && c->x86_model == 0x3f)
    > + return hsw_probetest();

    Firstly, isn't a probe already a test?

    Secondly, there's more HSW models:

    case 60: /* 22nm Haswell Core */
    case 63: /* 22nm Haswell Server */
    case 69: /* 22nm Haswell ULT */
    case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */

    Is this really only HSW server, or should they all be listed?


    \
     
     \ /
      Last update: 2015-06-15 16:21    [W:4.051 / U:0.992 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site