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    SubjectRe: [PATCH v4 11/20] clk: tegra: pll: Add code to handle if resets are supported by PLL
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    On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein@nvidia.com> wrote:
    > From: Bill Huang <bilhuang@nvidia.com>
    >
    > If a PLL has a reset_reg specified, properly handle that in the
    > enable/disable logic paths.
    >
    > Signed-off-by: Bill Huang <bilhuang@nvidia.com>

    Minor nit to add kerneldoc for params. Otherwise, LGTM.

    Reviewed-by: Benson Leung <bleung@chromium.org>

    > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
    > index b63ef31a2d7a..0146c91df635 100644
    > --- a/drivers/clk/tegra/clk.h
    > +++ b/drivers/clk/tegra/clk.h
    > @@ -217,6 +217,8 @@ struct tegra_clk_pll_params {
    > u32 lock_enable_bit_idx;
    > u32 iddq_reg;
    > u32 iddq_bit_idx;
    > + u32 reset_reg;
    > + u32 reset_bit_idx;

    Kerneldoc for these two.

    > u32 sdm_din_reg;
    > u32 sdm_din_mask;
    > u32 sdm_ctrl_reg;




    --
    Benson Leung
    Software Engineer, Chrom* OS
    bleung@chromium.org


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