Messages in this thread | | | Date | Mon, 04 May 2015 14:23:01 -0700 | From | "H. Peter Anvin" <> | Subject | Re: [RFC] Design for flag bit outputs from asms |
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On 05/04/2015 01:57 PM, Richard Henderson wrote: > > Sure. > > I'd be more inclined to support these compound conditionals directly, rather > than try to get the compiler to recognize them after the fact. > > Indeed, I believe we have a near complete set of them in the x86 backend > already. It'd just be a matter of selecting the spellings for the constraints. >
Whichever works for you.
The full set of conditions, mnemonics, and a bitmask with the bits in the order from MSB to LSB (OF,SF,ZF,PF,CF) which is probably the sanest way to model these for the purpose of boolean optimization.
Opcode Mnemonics Condition Bitmask 0 o OF 0xffff0000 1 no !OF 0x0000ffff 2 b/c/nae CF 0xaaaaaaaa 3 ae/nb/nc !CF 0x55555555 4 e/z ZF 0xf0f0f0f0 5 ne/nz !ZF 0x0f0f0f0f 6 na CF || ZF 0xfafafafa 7 a !CF && !ZF 0x05050505 8 s SF 0xff00ff00 9 ns !SF 0x00ff00ff A p/pe PF 0xcccccccc B np/po !PF 0x33333333 C l/nge SF != OF 0x00ffff00 D ge/nl SF == OF 0xff0000ff E le/ng ZF || (SF != OF) 0xf0fffff0 F g/nle !ZF && (SF == OF) 0x0f00000f
-hpa
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