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SubjectRe: [PATCH v9 1/10] x86, mm, pat: Set WT to PA7 slot of PAT MSR
On Wed, 13 May 2015, Toshi Kani wrote:
> This patch sets WT to the PA7 slot in the PAT MSR when the processor
> is not affected by the PAT errata. The PA7 slot is chosen to improve
> robustness in the presence of errata that might cause the high PAT bit
> to be ignored. This way a buggy PA7 slot access will hit the PA3 slot,
> which is UC, so at worst we lose performance without causing a correctness
> issue.
>
> The following Intel processors are affected by the PAT errata.
>
> errata cpuid
> ----------------------------------------------------
> Pentium 2, A52 family 0x6, model 0x5
> Pentium 3, E27 family 0x6, model 0x7, 0x8
> Pentium 3 Xenon, G26 family 0x6, model 0x7, 0x8, 0xa
> Pentium M, Y26 family 0x6, model 0x9
> Pentium M 90nm, X9 family 0x6, model 0xd
> Pentium 4, N46 family 0xf, model 0x0
>
> Instead of making sharp boundary checks, this patch makes conservative
> checks to exclude all Pentium 2, 3, M and 4 family processors. For
> such processors, _PAGE_CACHE_MODE_WT is redirected to UC- per the
> default setup in __cachemode2pte_tbl[].
>
> Signed-off-by: Toshi Kani <toshi.kani@hp.com>
> Reviewed-by: Juergen Gross <jgross@suse.com>

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>


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