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SubjectRe: [PATCH 02/10] perf/x86: Improve HT workaround GP counter constraint
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On Fri, May 22, 2015 at 5:59 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Fri, May 22, 2015 at 05:55:32AM -0700, Stephane Eranian wrote:
>> On Fri, May 22, 2015 at 5:53 AM, Peter Zijlstra <peterz@infradead.org> wrote:
>> > On Fri, May 22, 2015 at 05:35:14AM -0700, Stephane Eranian wrote:
>> >> On Fri, May 22, 2015 at 4:28 AM, Peter Zijlstra <peterz@infradead.org> wrote:
>> >> > On Fri, May 22, 2015 at 01:21:46PM +0200, Peter Zijlstra wrote:
>> >> >> @@ -821,8 +828,24 @@ int x86_schedule_events(struct cpu_hw_ev
>> >> >>
>> >> >> /* slow path */
>> >> >> if (i != n) {
>> >> >> + int gpmax = x86_pmu.num_counters / 2;
>> >> >> +
>> >> >> + /*
>> >> >> + * Do not allow scheduling of more than half the available
>> >> >> + * generic counters.
>> >> >> + *
>> >> >> + * This helps avoid counter starvation of sibling thread by
>> >> >> + * ensuring at most half the counters cannot be in exclusive
>> >> >> + * mode. There is no designated counters for the limits. Any
>> >> >> + * N/2 counters can be used. This helps with events with
>> >> >> + * specific counter constraints.
>> >> >> + */
>> >> >> + if (is_ht_workaround_enabled() && !cpuc->is_fake &&
>> >> >> + READ_ONCE(cpuc->excl_cntrs->exclusive_present))
>> >> >> + gpmax /= 2;
>> >> >> +
>> >> >> unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
>> >> >> - wmax, assign);
>> >> >> + wmax, gpmax, assign);
>> >> >> }
>> >> >>
>> >> >
>> >> > Hmm, I divide by 2 twice.. no wonder it doesn't quite work as expected.
>> >>
>> >> Yes, that's what I said. Other problem is, with no watchdog, measuring
>> >> a non-corrupting event is still multiplexing when more than 2 instances
>> >> are passed:
>> >> $ perf stat -a -C 0 -e r20cc,r20cc,r20cc,r20cc -I 1000 sleep 100
>> >>
>> >> I get 50% scheduling, only 2 out of 4 events scheduled at any time.
>> >>
>> >> There is nothing running on the sibling thread, so it should let me run with 4
>> >> instances as per your patch.
>> >
>> > Ah, I limited it to n/2 if either of the siblings has an exclusive event
>> > on.
>> >
>> But in my test case above, there was no exclusive event at all on either
>> sibling and yet it limited the non-excl to 2.
>
> I bet you tested the exclusive events earlier :-) Its one of the bugs,
> the n_excl accounting is leaking up. Once !0 it stays !0.

So you're saying intel_put_excl_constraint() does not do the --n_excl?
Could it be that the flags is not showing PERF_X86_EVENT_EXCL?
Cannot be related to cpuc_fake because you have it in both the ++
and -- functions.


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