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    Subject[PATCH 4.0 139/220] arm64: fix midr range for Cortex-A57 erratum 832075
    Date
    4.0-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Bo Yan <byan@nvidia.com>

    commit 6d1966dfd6e0ad2f8aa4b664ae1a62e33abe1998 upstream.

    Register MIDR_EL1 is masked to get variant and revision fields, then
    compared against midr_range_min and midr_range_max when checking
    whether CPU is affected by any particular erratum. However, variant
    and revision fields in MIDR_EL1 are separated by 16 bits, so the min
    and max of midr range should be constructed accordingly, otherwise
    the patch will not be applied when variant field is non-0.

    Acked-by: Andre Przywara <andre.przywara@arm.com>
    Reviewed-by: Paul Walmsley <paul@pwsan.com>
    Signed-off-by: Bo Yan <byan@nvidia.com>
    [will: use MIDR_VARIANT_SHIFT to construct upper bound]
    Signed-off-by: Will Deacon <will.deacon@arm.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/arm64/kernel/cpu_errata.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    --- a/arch/arm64/kernel/cpu_errata.c
    +++ b/arch/arm64/kernel/cpu_errata.c
    @@ -88,7 +88,8 @@ struct arm64_cpu_capabilities arm64_erra
    /* Cortex-A57 r0p0 - r1p2 */
    .desc = "ARM erratum 832075",
    .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
    - MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12),
    + MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
    + (1 << MIDR_VARIANT_SHIFT) | 2),
    },
    #endif
    {



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