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    Subject[PATCH 4.0 017/220] perf/x86/intel: Fix Core2,Atom,NHM,WSM cycles:pp events
    Date
    4.0-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Peter Zijlstra <peterz@infradead.org>

    commit 517e6341fa123ec3a2f9ea78ad547be910529881 upstream.

    Ingo reported that cycles:pp didn't work for him on some machines.

    It turns out that in this commit:

    af4bdcf675cf perf/x86/intel: Disallow flags for most Core2/Atom/Nehalem/Westmere events

    Andi forgot to explicitly allow that event when he
    disabled event flags for PEBS on those uarchs.

    Reported-by: Ingo Molnar <mingo@kernel.org>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Fixes: af4bdcf675cf ("perf/x86/intel: Disallow flags for most Core2/Atom/Nehalem/Westmere events")
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/kernel/cpu/perf_event_intel_ds.c | 8 ++++++++
    1 file changed, 8 insertions(+)

    --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
    @@ -557,6 +557,8 @@ struct event_constraint intel_core2_pebs
    INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
    INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
    INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
    + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
    + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
    EVENT_CONSTRAINT_END
    };

    @@ -564,6 +566,8 @@ struct event_constraint intel_atom_pebs_
    INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
    INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
    INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
    + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
    + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
    EVENT_CONSTRAINT_END
    };

    @@ -587,6 +591,8 @@ struct event_constraint intel_nehalem_pe
    INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
    INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
    INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
    + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
    + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
    EVENT_CONSTRAINT_END
    };

    @@ -602,6 +608,8 @@ struct event_constraint intel_westmere_p
    INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
    INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
    INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
    + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
    + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
    EVENT_CONSTRAINT_END
    };




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