Messages in this thread | | | Date | Mon, 18 May 2015 09:53:14 -0700 | Subject | Re: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration | From | Benson Leung <> |
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On Mon, May 18, 2015 at 4:03 AM, Bill Huang <bilhuang@nvidia.com> wrote: > This fixes bug in tegra_clk_register_pllss() which mistakenly assume the > iddq register is the PLL base address. > > Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Thanks for the quick fix. Reviewed-by: Benson Leung <bleung@chromium.org>
-- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org
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