Messages in this thread | | | Date | Thu, 14 May 2015 12:37:24 -0700 | Subject | Re: [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic | From | Benson Leung <> |
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On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@nvidia.com> wrote: > From: Bill Huang <bilhuang@nvidia.com> > > Super clock divider control and clock source mux of Tegra210 has changed > a little against prior SoCs, this patch adds Gen5 logic to address those > differences. > > Signed-off-by: Bill Huang <bilhuang@nvidia.com> > --- > v2: > - Fixed sclk divider address (0x370 -> 0x2c) > > drivers/clk/tegra/Makefile | 1 + > drivers/clk/tegra/clk-tegra-super-gen5.c | 150 ++++++++++++++++++++++++++++++ > drivers/clk/tegra/clk.h | 3 + > 3 files changed, 154 insertions(+) > create mode 100644 drivers/clk/tegra/clk-tegra-super-gen5.c
I've diffed clk-tegra-super-gen5.c and the existing clk-tegra-super-gen4.c, and there's a lot of code duplication here. They're the same pair of functions, with several small changes. Since the idea behind pulling out the super clock initialization into a common file was to reuse the same init, could we extend the super-gen4 file (rename if you have to) to support both gens instead?
-- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org
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