lkml.org 
[lkml]   [2015]   [May]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH] x86, mce, amd: Read mcgstatus before we log the error
On Wed, May 13, 2015 at 12:37:04PM -0500, Aravind Gopalakrishnan wrote:
> Code to read mcgstatus was introduced with patch 44612a3ac.
> However, that seems to have been accidentally removed in a3a529d10.
> Adding that back here.
>
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
> ---
> arch/x86/kernel/cpu/mcheck/mce_amd.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> index e99b150..7edfa4c 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> @@ -319,6 +319,7 @@ static void __log_error(unsigned int bank, bool threshold_err, u64 misc)
> return;
>
> mce_setup(&m);
> + rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);

Any meaningful bits in that MSR we wanna know when getting a
thresholding or deferred error? Are they even defined?

If yes, RIPV should always be 1b, EIPV too, MCIP can't be set.

-ENOMOREUSEFULBITS.

--
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
--


\
 
 \ /
  Last update: 2015-05-14 12:21    [W:1.416 / U:0.064 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site